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In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with...
Data stability is a primary concern in today's high performance memory circuits with deeply scaled transistors and power supply voltages. Recently proposed eight-transistor (8T) Static Random Access Memory (SRAM) cells offer enhanced data stability as compared to the conventional six-transistor (6T) SRAM cells by isolating the bitlines from data storage nodes during a read operation. Novel multi-threshold-voltage...
In Ultra Deep Sub Micron technology nodes, particularly 45nm and below, multiple power supplies are needed to achieve optimum performance. In such SoC's, level shifters play an important role in translating the signals from one voltage level to another. The conventional level shifters suffer from the contention between the pull up and pull down transistors which leads to the increase in delay and...
A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.
In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach,...
Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
In this paper the effects of multiplier architecture on the overall performance of the OFDM De-modulator for an UWB system are studied. The two commonly used VLSI multiplication algorithms, namely, the Baugh-Wooley algorithm and the Modified-Booth algorithm, are the candidates for this study. Partial product accumulation session can be found in both algorithms. There are two major classes of partial...
A 3-dimensional Vernier ring time-to-digital converter (TDC) is presented for the first time that greatly improves the measurement time and power consumption and achieves large detectable range and fine resolution simultaneously. The TDC prototype chip achieves 16.5-ps resolution and an 8-bit detectable range with 0.16 mm2 die area in a 0.13μm CMOS technology. The power consumption for the entire...
In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter...
Flip-flop is a vital component for high-performance and reliable deep-pipelined systems in digital microprocessors. In this paper, a new pre-discharge flip-flop (PDFF) is proposed. The performance advantage of PDFF comes from the fact that its critical path is reduced significantly to only three transistors in the worst case. A detailed comparison is carried out between the proposed PDFF and previous...
Analog to digital converters are an important system building block, as an interface between analog and digital world. Parallel comparator type (flash) ADCs is used in high speed, low resolution applications. This paper presents the characterization analysis of CMOS flash ADCs under Threshold inverter technique for different resolutions, the effect of the VLSB (step size) of the comparator on the...
We present a UWB two-way communication system with novel PHY and MAC layers, for low-rate communications with multitude of low-cost devices in ultra low power consumption. The system features a novel multiple access protocol called interleaved impulse radio. In this simple protocol the transmission is done in short bursts of about 100 ns with large gaps between them. During the gaps other users can...
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock...
This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous...
Pulse-triggered flip-flops are widely used in microprocessors in recent years due to their high performance. JK flip-flops are more powerful than D flip-flops. However, designs of pulse-triggered JK flip-flops are seldom mentioned. Generally, JK flip-flops are designed on the basis of D flip-flops, and have more power consumption and larger delay than D flipflops. An explicit-pulsed double-edge triggered...
High data rates and increased digitization require A/D converters with high dynamic range and bandwidth. In combination with low power consumption they are key for broadband wireless systems. A single bit continuous-time DeltaSigma modulator with 10 MHz signal bandwidth avoiding high speed DEM circuits in 1.2V 90 nm digital CMOS is presented. It achieves an SNDR of 65 dB while consuming only 6.8 mW...
A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7 bits TDC prototype realized in 65 nm CMOS technology is presented. The chip has a resolution of 4.8 ps with a power consumption of 1.7 mW at a conversion rate of 50...
This paper presents a high performance 16times16 bit 2's complement multiplier using MOS current mode logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mum CMOS...
This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator...
This work presents a low-power multiplier using a dynamic-range determination (DRD) unit and a modified upper/lower left-to-right (ULLR) structure in the partial-product summation (PPS) unit. Prior to executing a multiplication, effective dynamic ranges of two input data are estimated by the DRD unit to determine that these input data with smaller and larger dynamic ranges are multiplier and multiplicand...
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