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As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
To securely exchange data over public networks, such as the Internet, organizations often utilize Virtual Private Networks (VPNs). However, relying on these potentially large overlay networks makes them vital targets for Denial-of-Service(DoS) attacks. Thus, recent approaches for VPN auto-configuration address DoS resistance by employing distributed management algorithms. Nevertheless, there is no...
This paper presents a soft error hardened latch suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes, external logic, as well as the pulse generator circuit. The hardening method is based on redundancy to protect internal nodes and filter out transients resulted from combinational logic. It also uses redundant clocking technique which...
Moving into the era of nanoscale devices, reliable clock distribution becomes a challenging problem due to the growing impact of process variations. This paper deals with this difficulty, especially on implementing useful clock skew. One possible robust way is by using programmable delay elements (PDEs) since PDEs can be adjusted after fabrication. However, with this benefit, using PDEs takes large...
With CMOS technology shrinking to nanoscale regime, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for...
The semiconductor industry is facing a critical research challenge: design future high performance and energy efficient systems while satisfying historical standards for reliability and lower costs. The primary cause of this challenge is device and circuit parameter variability, which results from the manufacturing process and system operation. As technology scales, the adverse impact of these variations...
Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesize a constraint guaranteeing a correct...
Fine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each voltage/ frequency island must be taken into account to optimize the circuit. This paper focuses on the control for the frequency actuator. An optimal and robust saturated...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
As a major sequential logic element, D flip-flop is an indispensible cell in logic cell library. In this paper, we proposed two improved sub-threshold D flip-flop circuits (mTGMS and emC2MOS D flip-flop) after conducting robustness analysis of several typical flip-flop circuits. Using SMIC 0.18um CMOS technology, the simulation results show that the minimum work voltage of our proposed mTGMS and emC...
This paper presents a design methodology for robust and low-energy clock networks for ultra-low voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that...
In this paper, an adaptive and robust monitoring approach for Wireless Sensor/Actuator Network (WSAN) environments is proposed. The main problem under investigation is the monitoring of the status of WSAN devices in an environment where the clocks of the devices are not well synchronized (asynchronous communication). The main contribution is the proposed adaptive virtual timer, for the server node,...
Lessons learnt during the deployment of transition scan content on an Intel® Itanium® server microprocessor design and its use for electrical debug and defect screening in high-volume manufacturing are described. While many publications in the area of transition scan show it being practiced as an efficient defect screening tool, only a minority of these designs were high-performance microprocessor...
This paper presents a true single-phase clock (TSPC) flip-flop that is robust against radiation-induced single event upsets (SEUs) or soft errors. The flip-flop consists of an input stage that uses a single phase clock to pass the data to a storage unit at the positive edge of the clock. The single phase clock enables designing power-efficient and easily-routed clock-tree and reducing the NBTI effect...
The time-dependent degradation (aging) of device characteristics caused by Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI) are one of the major threats to the reliability of nanoscale digital CMOS designs. To address this challenge, a novel built-in aging “detection” and “compensation” technique is proposed. Performance degradation is detected using a novel area- and power-efficient...
Multiple input switching (MIS) on off-path inputs is known to increase the delay through a gate. However, due to the complexity of incorporating MIS in timing analysis, design flows typically ignore the effect of MIS. Test tools also do not attempt to maximize the off-path switching to maximize delays through a path. In this paper we study the impact of not maximizing the switching on the off-path...
Dealing with process and environmental variability became a great challenge for IC designers in the latest technology nodes. Digital circuits are designed in such a way that timing and power constraints are respected with minimum resource usage, to do that tight power and timing margins are desired. If process and environmental variability are not accounted during the design stage power and timing...
The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs...
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