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This paper presents a novel architecture of Asynchronous Pipelined Analog to digital converter with emphasis on elimination of external clock for integrated self-triggered sensor based applications. The main innovative feature of the proposed pipelined ADC is that it operates without any external clock signal and performs conversion of the analog input like a combinational logic. Complete digital...
With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental...
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same...
In recent years, many research results have discussed the mixed static-domino high-speed circuit. However, most research neglects to discuss how to implement their results. Silicon Intellectual Property plays very important roles in the design of current complex integrated circuits. In this paper, we construct a new pipeline mixed static-domino high-speed circuit synthesized methodology. The cell-based...
In this paper, we propose several design approaches to extend useful voltage scaling (i.e. voltage scaling with net energy savings) beyond the conventional limit, which is imposed by the rapid increase of leakage energy overhead in ultra low voltage regimes. We are able to achieve such extra voltage scaling and thus energy savings without compromising performance and variability through minimizing...
Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
A high-speed dual-phase domino circuit design with high performance and reliable characteristics is proposed. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64-bit high-speed multiplier with a built-in performance adjustment mechanism has been successfully validated using TSMC 0.18um CMOS technology. The test chip shows a...
Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (∼200mV above...
A design, implementation and evaluation of low power accelerator CMA-2 were introduced. Evaluation result with real chip shows that the maximum energy efficiency is 233.7 MOPS/mW.
The Razor dynamic voltage scaling approach uses in situ error-detection and correction of timing errors to reclaim safety margins for improved energy-efficiency in digital circuits. In this paper, we propose the use of a time borrowing window on critical logic paths, over which timing errors can resolve safely without an explicit replay mechanism. We demonstrate that time borrowing can be incorporated...
Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat it for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) to expose variation and its effects to the software stack...
Near-threshold operation has emerged as a competitive approach for energy-efficient architecture design. In particular, a combination of near-threshold circuit techniques and parallel SIMD computations achieves excellent energy efficiency for easy-to-parallelize applications. However, near-threshold operations suffer from delay variations due to increased process variability. This is exacerbated in...
Voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. We propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network...
High performance implementation of 2D digital filters are highly desired in many applications for real-time processing. In this paper, a multiprocessor realization of a 2D denominator separable digital filter is implemented in Altera Stratix III FPGA. The implementation achieves a data throughput equivalent to one multiplication and two additions, plus one clock cycle. It has been found that the maximum...
“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking...
The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism...
Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict...
To resolve the latency problem of implementing Montgomery modular multiplication algorithm using the linear systolic array, this paper proposes the improved Montgomery algorithm, and improves the systolic array by combining the long carry save adder (CSA) structure. This paper also proposes a series of methods to optimize the critical path and a non-waiting modular multiplication strategy which can...
Today's FPGAs are capable of performing complex Image Processing schemes. In this paper we introduce a Configurable Zero Stall Image-Processing Pipelined Architecture. We define the handshake and discuss limitation resulting from configurability and complexity. We then present our solution for these issues allowing a simple yet effective circuit where no delay is introduced even though the output...
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