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Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
This paper presents an architecture of system Verilog assertions (SVA) synthesis compiler, which translates the un-synthesizable System Verilog assertions, into synthesizable equivalent Verilog modules, in order to convert them to digital hardware circuits, used to watch how the running design performs. The proposed architecture is based on two main rules: "Simple compiler structure" and...
With the help of assertion based verification, engineers nowadays can check a digital design against its specification more easily and precisely. What's more, assertion descriptions can be synthesized into hardware, which makes post-fab on-line monitor possible. But most of the paper does not consider waveform capture and off-line replay features that can help engineers further analyze captured waveforms...
Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed...
In this work we propose the rather new approach to synthesize properties formulated in verification languages, in particular PSL, down to hardware level. Such flow can be useful especially for safety-critical applications to automatically generate runtime monitors at little additional design efforts. Existing assertion synthesis tools from both academia and industry are presented as well as evaluation...
The rise of network speeds to tens of gigabits per second poses a challenge to develop packet processing applications that can cope with such bit rates. Therefore, the need for a suitable open source system that can be used as a prototype platform to test new network functionality while ensuring line-rate processing, accurate timestamping, and reduced power consumption has become evident. All these...
In this paper proposed is a cost-efficient architecture of FIR filter for portable digital spectrum analyzers. In order to reduce the hardware complexity, we split an FIR filter into multiple stages, which share the hardware resources such as multipliers and adders with one another. It makes sense because portable spectrum analyzers should be implemented with very low hardware costs and the real-time...
In this paper we present a novel concurrent BIST scheme termed as “Register based Recording and Windowed Playback”. We propose a method to test digital ICs during normal operation. The hardware used for online-offline testing observes the normal inputs and eliminates those from the test set. Unlike the previous method (SWiM), a register is used to record the normal inputs in the online mode and in...
Within the aviation industry RTCA DO-254 is the design assurance process for safety-critical airborne electronic hardware development. Safety-critical hardware (DAL A or B) requires the application of additional advanced verification techniques such as Elemental Analysis to ensure that elements of the design are adequately verified. This paper compares the verification processes currently used in...
A simplified hardware verification platform based on layered approach is implemented using SystemVerilog. SystemVerilog unifies several proven hardware design and verification languages in the form of extensions to Verilog HDL. The importance of a verification platform based on OOP technique is increasing for high-level functional verification. The proposed platform consists of components such as...
Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design...
The paper proposes DDPSL (Drag and Drop PSL) a template library and a tool which simplifies the definition of PSL (Property Specification Language) formal properties by exploiting PSL-based templates. DDPSL allows users not expert in formal methods to define PSL properties by dragging and dropping logical and temporal operators, and variables from the design under verification (DUV) into predefined...
Aspectual Feature Module (AFM) is a newly proposed methodology for the development of software product lines. Considering the similar problems of product line development in hardware (e.g. how to exploit the similarity between products in product line), this paper suggests the application of AFM in Hardware Description Languages (HDL). We propose the possible applications, including the usage of incremental...
This work presents a new method for hardware functional verification through parallel co-simulation within complex systems using PLI as a mechanism of interface between hardware (HW) and software (SW). This method consists in the HW/SW parallel simulation using a transparent communication between these modules provided by a handshake mechanism that ensure the synchronism between the parts. The discussion...
Aiming at the requirements of real-time ability and good observability of result-checking in IC functional verification, a method was proposed to generate monitors automatically. Based on the requirements of the design property to be monitored, a sub-set was defined from the Property Specification Language (PSL), so that the objects to be monitored can be formally described. Based on the formal descriptions,...
This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current...
High-Level Languages (HLLs) for FPGAs (Field-Programmable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages (HDLs). However, this abstraction is typically accompanied by some loss of performance...
We describe the Kiwi parallel programming library and its associated synthesis system which is used to transform C# parallel programs into circuits for realization on FPGAs. The Kiwi system is targeted at making reconfigurable computing technology accessible to software engineers that are willing to express their computations as parallel programs. Although there has been much work on compiling sequential...
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