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This paper presents a novel ATPG and test compression algorithm based on Pseudo-Boolean (PBO) optimization. Similarly to SAT-based ATPGs, the test for each fault is represented implicitly as a PBO instance. The optimization process solves the problem of maximizing the number of unspecified values in the test. A novel don't care aware circuit-to-PBO conversion procedure is presented. The obtained unspecified...
It is known that EDA tools produce results of different quality dependent on seemingly neutral details in the input. We bring further results in this direction, which show that the differences can impair any quantitative comparisons of the tools. To gain qualitative insight, we present a stochastic model of result quality based on Gaussian Mixtures. We show on three case studies how these models help...
We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss...
In this paper, a method for constructing sequences of reversible functions of large number of variables is presented. First, by using our database of all minimal reversible circuits for 3-variable reversible functions, and our tool for designing minimal circuits for 4-variable reversible functions, circuits with structural regularities are searched for. The aim is to find a pair, 3- and 4-variable...
A subclass of efficient simulation-based sequential test generation procedures are guided by information about primary input values that effective test subsequences should use. This information is represented by a primary input cube c. In all the earlier procedures that are based on this concept, the computation of c is fault-independent. This paper introduces an approach for a fault-dependent computation...
This work proposes an ESOP-based technique for the synthesis of reversible circuit using a paired cube approach. In this method, initially we provide an ESOP as input and generate an optimized cube structure. Next, the pairing of ESOP cubes based on their structural similarity is performed to design improved reversible circuit using Toffoli gates. Experimental result shows that the paired cube synthesis...
Simulation-based verification is still the state-of-the-art when checking the correctness of complex Systems-on-Chips. In particular, constraint-based simulation is popular, since here dedicated stimuli are generated which trigger certain corner-case behavior. However, to the best of our knowledge, only heuristic methods have been introduced so far. In this paper, we propose an approach that determines...
This paper reports on a method of the construction of new difficult benchmarks for reversible logic synthesis. It is shown how to extrapolate 3- and 4-variable reversible functions implemented by gate count minimal circuits having regular structure. In this way sequences of reversible functions of an arbitrary number of variables have been constructed for which we have built minimal circuits implementing...
Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss...
One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time. Conventional gate-level automatic test pattern generators (ATPGs) and Satisfiability (SAT) solvers work on instances containing...
In order to gain market share in today's competitive high-tech industry, fast time-to-market (TTM) is one of the key factors for the success of a product. Since pre-silicon verification cannot be applied exhaustively as the size and complexity of the integrated circuit design increases, post-silicon validation becomes crucial to capture bugs and design errors that escape from the pre-silicon verification...
Globalization of semiconductor design and manufacturing has led to a concern of trust in the final product. The effect of any modifications made by an adversary can be catastrophic in critical applications. Because of the stealthy nature of such insertions, it is extremely difficult to detect them using traditional testing and verification methods. In this paper, we propose a novel technique for detection...
This paper proposes a novel minimal test point insertion methodology that provisions a provably complete detection of hardware Trojans by noninvasive timing characterization. The objective of test point insertion is to break the reconvergent paths so that target routes for Trojan delay testing are specifically observed. We create a satisfiability-based input vector selection for sensitizing and characterizing...
This paper proposes Hardware Trojan (HT) placement techniques that yield challenging HT detection benchmarks. We develop three types of one-gate HT benchmarks based on switching power, leakage power, and delay measurements that are commonly used in HT detection. In particular, we employ an iterative searching algorithm to find rarely switching locations, an aging-based approach to create ultra-low...
Modern synthesis flows apply a series of technology independent optimization steps followed by mapping algorithms which bind the optimized network to a specific technology library. As the exact solution of the mapping problem is computationally intractable, algorithms used in practice use heuristic, typically tree-based approaches. The application of these algorithms results in mapped but suboptimal...
For a design with multiple functional errors, multiple patches are usually needed to correct the design. Previous works on logic rectification are limited to either single-fix or partial-fix rectifications. In other words, only one or part of the erroneous behaviors can be fixed in one iteration. As a result, it may lead to unnecessarily large patches or even failure in rectification. In this paper,...
Input Vector Monitoring Concurrent Built-In Self Test (BIST) schemes provide the capability to perform testing while the Circuit Under Test (CUT) operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. In this paper a novel input vector monitoring concurrent BIST scheme is presented, that reduces considerably the imposed hardware overhead compared...
Three-input majority gates and inverters form the basic Boolean primitive logic blocks of quantum cellular automata (QCA) circuits. Ideally, an optimized QCA design should have minimal number of gate counts and logic levels. However, existing majority gate logic synthesis methods based on three-feasible networks often result in inefficient use of majority logic gates. In this paper, we propose an...
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