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A power-efficient analog beamforming embedded SAR ADC for ultrasound imaging systems is presented. It is constructed from multiple sub-beamforming SAR ADCs, which sequentially perform analog beamforming and analog-to-digital conversion for an assigned focal point on a scan-line. Power is saved because these operations are carried out in the charge domain without a summing op-amp. This is realized...
High Efficiency Video Coding (HEVC) is the new video compression standard. A novel optimized architecture of Integer Motion Estimation (IME) for HEVC processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 43 fps (frames per second) with a frequency of 142 MHz and a latency of 402 clock cycles. The proposed design has been synthesized and simulated...
Modular multiplication, addition, and subtraction being the core operation of Elliptic curve public(ECC) system, the decrease of area and the merging of structure have been a hot topic in recent years. This paper first analyzes the difference between multiplication type and addition type of modular multiplier. Then, Combined with the structural characteristics of the modular adder, and mixing modular...
A proposed phase-interpolator (PI) based hybrid digital pulse width modulator (DPWM) effectively resolves the trade-off between resolution and power consumption. Conventional DPWM delay-line-based architectures suffer from high power consumption limited delay time per delay-tap due to process technology, while the proposed solution replaces the delay line with a PI featuring sub-gate-delay resolution...
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for an intra-panel interface is presented. Phase emphasis is introduced into the final 2:1 stage of a 20:1 serializer to reduce the data-dependent jitter without increasing IO capacitance, by making the transition timing depend on previous data. This is combined with LVDS channel drivers which control the common-mode voltage...
In this paper, implementation of an energy-efficient, low power, noise immune 4×4 Vedic Multiplier is proposed. The adder circuit used as building block in the multiplier unit is designed using semi-domino logic. The proposed multiplier unit has its benefits in terms of power consumption, delay, Energy-Delay-Product and UNG. This circuit exhibits a lower EDP of 2.88 Tena Micro to 27.97 Tena Micro,...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
Polar codes are a family of error correcting codes that achieves the symmetric capacity of memoryless channels when the code length N tends to infinity. However, moderate code lengths are required in most of wireless digital applications to limit the decoding latency. In some other applications, such as optical communications or quantum key distribution, the latency introduced by very long codes is...
In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
A novel architecture of Integer Motion Estimation (IME) for High Efficiency Video Coding (HEVC) processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 45 fps (frames per second) with frequency of 96.4 MHz and latency of as low as 260 clock cycles. The proposed design has been implemented by Xilinx ISE 13.1 using Virtex-7 28nm technology.
A multi-carrier modulation technique is Orthogonal Frequency Division Multiplexing (OFDM) which divides the available spectrum into many carriers. The spectrum efficiently uses in OFDM compared to FDMA by spacing the channels much closer together. All carriers in OFDM orthogonal to one another to prevent interference between the closely spaced carriers. The objective of this work is to study and design...
This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show...
This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes...
Implementing elliptic curve point multiplication (ECPM) based on residue number system (RNS) can efficiently use FPGA resources. In this paper, we propose a modular reduction method, where a kind of RNS pair is selected to achieve fast reduction. Our reduction method mainly needs several parallel additions while the reduction unit of previous designs require two multiplications which are computed...
Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. The Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on Field Programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given...
In this paper we present a k-means clustering algorithm for the Versat architecture, a small and low power Coarse Grained Reconfigurable Array (CGRA). This algorithm targets ultra low energy devices where using a GPU or FPGA accelerator is out of the question. The Versat architecture has been enhanced with pointer support, the possibility of using the address generators for general purposes, and cumulative...
The Internet of Things revolution requires long-battery-lifetime, autonomous end-nodes capable of probing the environment from multiple sensors and transmit it wirelessly after data-fusion, recognition, and classification. Duty-cycling is a well-known approach to extend battery lifetime: it allows to keep the hardware resources of the micro-controller implementing the end-node (MCUs) in sleep mode...
With recent advances and demands for data storage, new architectures for data controller chips are picking pace. Accordingly, the test methodologies for such chips are also becoming crucial since the large shipping volumes of those chips demand very few field returns. Along with the advances there is a need for a robust test strategy with some novel techniques which can be enabled to test the SOC...
CPU-GPU heterogeneous systems are emerging are emerging as architectures of choice for high-performance energy-efficient computing. Designing on-chip interconnects for such systems is challenging: CPUs typically benefit greatly from optimizations that reduce latency, but rarely saturate bandwidth or queueing resources. In contrast, GPUs generate intense traffic that produces local congestion, harming...
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