The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
String matching hardware engines generally utilize Ternary Content Addressable Memories (TCAMs). Although TCAM-based solutions are fast, they are expensive and power hungry. This paper proposes a high-performance memory-less architecture for string matching called Split-Bucket. It offers a performance comparable to TCAM-based solutions. Moreover, it is reconfigurable and scalable to the size of the...
We propose a design flow for automatic generation of hardware sandboxes. Our tool, the Component Authentication Process for Sandboxed Layouts (CAPSL), generates sandboxes capable of detecting trojan activation and nullifying potential damage to a system at run-time. Our approach captures the behavioral properties of non-trusted IPs with formal models that are translated to checker automata and implemented...
High level synthesis tools are an attractive option for rapid prototyping and implementation of hardware designs. In this paper we present a case study of using such a tool for the design and implementation of an FFT core for use in a wireless modem. The optimizations used for directing the conversion of C code to hardware are discussed and the impact of the different directives is analyzed. The resulting...
As a method for edge-preserving or noise-reducing, a bilateral filter is widely used. However, because every pixel in a filtering window needs a separate Look-Up Table (LUT) for the parallel processing, its hardware implementation is still bulky. In this paper, we propose Similar Weight Grouping (SWG) which maps multiple indexes with a similar value onto a single index and Zero Value Suppression (ZVS)...
This letter presents a novel framework for the design of adjustable reconfigurable partitions for the placement of variable-sized IP cores on embedded reconfigurable systems. It enables the rapid and easy to use methodology for the generation of adaptive computation and communication infrastructure for partial dynamic reconfiguration. The methodology allows an adaptable partition and efficient resource...
An inverse kinematics IP (Intellectual Property) for six-axis articulated manipulator is investigated in this paper. Firstly, the formulation of the inverse kinematics for six-axis articulated manipulator is derived. Secondly, the computation algorithm and its hardware implementation of some key trigonometric functions are described. Thirdly, the IP design of inverse kinematics is illustrated and...
Heterogeneous multicore platform has been widely used in various areas to achieve both power efficiency and high performance. This paper proposes a FPGA implementation of a hardware scheduler supporting parallel dataflow execution on heterogeneous multicore platform. The scheduler has the capability to explore potential parallelism, leading to a high acceleration of dependence-aware applications....
Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially...
As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to...
Because of the rapid growth of both traffic and links capacity, the time budget to perform IP address lookup on a packet continues to decrease and lookup tables of routers unceasingly grow. Therefore, new lookup algorithms and new hardware platform are required to perform fast IP lookup. This paper presents a new scheme on top of the NetFPGA board which takes advantage of parallel queries made on...
Packet classification plays a crucial role for a number of network services such as policy based routing, firewalls and traffic billing to name a few. However, classification can be a bottleneck in the above mentioned applications if not implemented properly and efficiently. In this work we propose PCIU, a novel algorithm, which improves upon previous published algorithms. PCIU provides lower pre-processing...
IP address lookup is a fundamental operation in packet forwarding. Using multi-level index tables to find out the next-hop value is an attractive approach due to its simplicity. However, memory efficiency is relatively low because prefixes are sparsely distributed in the address space. In this poster, we shall outline a new approach to construct memory efficient index tables based on a technique called...
Hashing is popularly adopted when it comes to a large scale of IP flows. This paper mainly focused on the lookup performance of content addressable memory aided hash table (CAHT). High throughout is available with minimized average memory access number. By rational approximation, the paper provided the lower bound on average memory access number over CAHT. When the hash is perfect hash or nearly to...
Internet line speeds are expected to reach 100 Gbps in a few years. To match these line rates, a single router line card needs to forward more than 150 million packets per second. This requires a corresponding amount of longest prefix match operations. Furthermore, the increased use of IPv6 requires core routers to perform the longest prefix match on several hundred thousand prefixes varying in length...
The increasingly more stringent performance and power requirements of Internet routers call for scalable IP lookup strategies that go beyond the currently viable TCAM- and trie-based solutions. This paper describes a new hash-based IP lookup scheme that is both storage efficient and high performance. In order to achieve high storage efficiency, we take a multi-hashing approach and employ an advanced...
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel architecture on reconfigurable hardware platform. A partial reconfiguration may be needed for a small fraction of route updates. Prefixes can be added or removed at a rate of 2 million updates per second, including this hardware...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.