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We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
Run-time partial reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use direct memory access (DMA), master (MST) burst, and a dedicated block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA...
Design productivity is one the most important challenge facing future generation multiprocessor system on chip (MPSOC). The modeling of dozens of interconnected IPs with distributed memories implies intensive manual EDA based design activity. We propose to improve design productivity by raising IP reuse to small scale multiprocessor IP combined with fast extension techniques for system level design...
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