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A simple array-based test structure has been developed to characterize AC variability in deeply scaled MOSFETs. Each test structure consists of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit. The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed...
The performance analysis of the Fixed Duty Ratio (FDR) and Adaptive Gate Drive (AGD) in high frequency gate driver design is analyzed in this paper. FDR is well known for its simplicity. The limitation of this control scheme requires a longer delay time before the next switching can be executed. As for AGD, the delay adjustment can be controlled for different MOSFET. However, it is hard to detect...
The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.
We propose and numerically analyze three novel reconfigurable logic cells (reconfigurable NAND/NOR, NAND/XNOR, and XNOR/XOR cells) based on single-electron transistor (SET) and MOSFET hybrid circuits. These reconfigurable cells can work normally at room temperature with high flexibility and performance. Compared with pure MOSFET circuits, the cells proposed in this paper can flexibly realize many...
A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T relay design is that it provides a means for electrically adjusting the switching voltage; as a result, a 4T relay can mimic the operation of either an n-channel or p-channel MOSFET. Fabricated 4T relays exhibit good on-state current (Ion > 700 ??A for VDS = 1 V) and zero off-state...
A variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed in this paper for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
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