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Convolutional Neural Networks (CNNs) are one of the most successful deep machine learning technologies for processing image, voice and video data. CNNs require large amounts of processing capacity and memory, which can exceed the resources of low power mobile and embedded systems. Several designs for hardware accelerators have been proposed for CNNs which typically contain large numbers of Multiply...
Today's applications for HW/SW-systems, such as the Internet-of-Things, often demand SoC architectures where sophisticated firmware is running on fairly simple processors. Designers face the challenge of meeting high requirements for these systems regarding their efficiency and dependability under severe cost constraints. Targeting such applications this paper presents a new technique to generate...
As the development of a viable quantum computer nears, existing widely used public-key cryptosystems, such as RSA, will no longer be secure. Thus, significant effort is being invested into post-quantum cryptography (PQC). Lattice-based cryptography (LBC) is one such promising area of PQC, which offers versatile, efficient, and high performance security services. However, the vulnerabilities of these...
System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the complexity in understanding different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design...
Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates for industrial-size software running upon hardware platforms comprising high-performance features. MBPTA relies on the randomization of timing behavior (functional behavior is left...
Timing is a key non-functional property in embedded real-time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however complicates timing analysis. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at analysing the timing behaviour of ERTS deploying complex hardware features such as caches...
Measurement-Based Probabilistic Timing Analysis (MBPTA) derives WCET estimates for tasks running on processors comprising high-performance features such as caches. MBPTA's correct application requires the system to exhibit certain timing properties, which can be achieved by injecting randomisation in the timing behaviour of the task under analysis. However, existing software-randomisation techniques...
Probabilistic Timing Analysis (PTA), especially its measurement based variant (MBPTA), has shown to be competitive with state-of-the-art timing analysis techniques. The use of MBPTA to analyse the timing behaviour of safety-critical systems rests on its ability to derive trustworthy WCET bounds. This ability depends on the soundness of the MBPTA method per se, as well as on the satisfaction of safety...
Due to the trend of outsourcing designs to foundries overseas, there has been an increasing threat of malicious modifications to the original integrated circuits (ICs), also known as hardware Trojans. Numerous countermeasures have been proposed. However, very little effort has been made to design-time strategies that help to make test-time or run-time detection of Trojans easier. In this paper, we...
Computer architects are increasingly interested in evaluating their ideas at the register-transfer level (RTL) to gain more precise insights on the key characteristics (frequency, area, power) of a micro/architectural design proposal. However, the RTL synthesis process is notoriously tedious, slow, and errorprone and is often outside the area of expertise of a typical computer architect, as it requires...
This paper presents an industry experience and research-based analysis of issues that the deployment of PTP as a service is facing in the finance industry, based on real life examples from a global stock exchange operator. It aims to summarise over three years of author's experience with deploying PTP, highlighting the most common problems encountered: standard specific, implementation specific and...
Testing involves applying stimulus to a device, called the Unit Under Test (UUT), and evaluating the measured response against the expected values. Traditional systems use discrete instruments to supply the stimulus and measure the response, but most devices are part of a larger system and may be a component of a closed control loop. Many devices are designed to respond to the inputs by generating...
Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technologies lead to high failure rates, thus lowering survivability of chips to unacceptable levels for CRTE systems. This paper presents SESACS architecture...
The Complex Device Driver is a loosely coupled container, where specific software implementations can be placed. The only requirement to the software parts is that the interface to the AUTOSAR system has to be implemented according to the AUTOSAR port and interface specifications. The purpose of the Complex Device Drivers is to fulfill the special functional and timing requirements for handling complex...
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