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Low-offset and low-noise operational amplifiers (OpAmps) are essential for precision measurement systems. Applications such as precision weigh scales, sensor front-ends, bridge transducers, interfaces for thermocouple sensors, and medical instrumentation require amplification of low-level signals with high closed-loop gain and low noise. An OpAmp with high precision and fast response enables more...
As device dimensions and supply voltage are shrinking, the design of high-speed and high-resolution analog-to-digital converters (ADCs) is getting more and more challenging. Since the shrinking device sizes enable high-speed and low-power digital circuits, there has been a trend to use digital circuits to estimate and correct for the analog circuit nonidealities (i.e. calibrate) to realize high-performance...
This brief presents a 10-bit 100-MS/s 1.2-V dual-channel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel...
In this paper, two techniques aiming to improve the performance of the switched-capacitor correlated-level-shifting technique are introduced. While boosting the equivalent opamp dc gain, this technique uses three clock phases. First, a time-shifted two-phase sampling approach is introduced with the addition of another set of sampling capacitors. However, this configuration has the disadvantages of...
A reconfigurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and programmable gain amplifiers. Each block employs a zero-crossing based circuit for easy reconfigurability and power efficiency. Configured as a 10-bit ADC, the chip consumes 1.92mW at 50MSPS with ENOB of 8.02b and FOM of 150fJ/conversion-step. A third order Butterworth filter is also demonstrated...
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. In the 8-bit mode, measured effective...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
A digital foreground self-calibration method, bases on the existing off-line calibration algorithm is presented. This work extends it to correct nonlinear effects of the op amps. It eliminates both linear and nonlinear errors, such as capacitors mismatch, comparator offset, finite op amp gain error, and op amp nonlinearity. The simulation shows that this work gives great improvements of 38.25dB and...
A 10-bit 300 MSample/s pipelined analog to digital converter (ADC) using time-interleaved successive approximation register (SAR) ADC in the first stage is presented. By replacing the front-end pipelined stages with energy-efficient SAR-ADC, power hungry sample-and-hold amplifier can be removed and rail-to-rail input can be used. In addition, feedback factor of the first MDAC can be increased, which...
In this paper, an 8-bit, 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-μm CMOS process. Simulated effective number of bits (ENOB) of the ADC is 7.09 with...
This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also...
This paper describes a mixed mode background calibration technique for pipeline analog-to-digital converter (ADC). The proposed calibration scheme uses an insignificant, low-speed, low-power, high-resolution sigma-delta ADC to determine error in digital domain. The calibration technique calibrates capacitor mismatch as well as finite opamp dc gain, while the digital redundancy compensates for comparator...
This paper propose a suitable structure to increase the gain and speed of low-voltage amplifiers by means of modifying the first stage of the Folded-Cascode (FC) structure and exploiting class AB amplifier with active load at the second stage. In spite of the fact that cascode structures increase the output impedance, we make an extra pole in the transfer function of the network to raise the transconductance...
A fully differential, low-power, area-efficient analog to digital converter has been designed and simulated for implantable neural signal recording systems. Proposed ADC consisted of an analog stage, similar to a pipeline converter stages but reused it to extract the final effective bits. This paper presents a 9-bit 1-MSample/s analog to digital converter with stage reused technique that has been...
The pipelined architecture is one of the most popular analog-to-digital converter (ADC) architectures. Various circuit nonidealities such as finite opamp gain and mismatch in capacitors limit the pipelined ADCpsilas performance. In this paper, a new technique for the calibration of interstage gain errors in pipelined ADCpsilas are described. The proposed calibration scheme uses a slow but accurate...
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