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A typical hardware design flow starts with the description of a design at a particular level of abstraction which is then synthesized to the corresponding low-level implementation of the abstract description. For example, RTL (Register Transfer Level) descriptions of hardware designs are synthesized to gate-level implementations, which are further synthesized to the physical level. Thus, hardware...
High-level synthesis of hardware designs has been shown to be possible from a variety of high-level HDLs which are used to specify the behavior of the designs at a level of abstraction above RTL. Hardware descriptions written using such HDLs are passed as inputs to high-level synthesis tools to generate the RTL code. Below, we briefly discuss some of the high-level specification languages and corresponding...
A CDFG-based high-level synthesis takes a behavioral specification of a design as input and generates the corresponding RTL code. Apart from the specification, other inputs to a high-level synthesis process can be an optimization function, design constraints, and a module library representing the available components at RTL. The goal of the synthesis process is to generate an RTL design that implements...
Hardware implementations generated from CAOS can exploit the parallelism germane in the computation and execute maximal set of actions concurrently in order to reduce the latency of the design. The concurrent execution of actions may result in high peak power and dynamic power consumption in the hardware generated from such specifications. Peak power becomes an issue if large number of actions are...
As discussed in Chapter 4, the optimization problems germane in the low-power CAOS-based synthesis process are NP-hard. Thus, heuristics are needed to solve these problems efficiently. In this chapter, we discuss a class of heuristics targeting the reduction of peak power and average dynamic power in the scheduling and allocation phases of the CAOS-based synthesis process. We show some numerical examples...
Scheduling, allocation and binding are three important phases of a CDFG-based synthesis process. These phases are interdependent and can be performed in different orders depending on the design flow. In some cases, two or more phases can also be performed simultaneously. Such simultaneous execution of these phases during a synthesis process will result in a solution which is globally optimal. However,...
Dynamic power is an important component of the power consumption of a hardware design. In this chapter, we present two algorithms that target the reduction of dynamic power during the CAOS-based synthesis process and produce RTL that can be synthesized into power-efficient hardware. We also present experimental results to show that when a CAOS specification is compiled using these algorithms, the...
In hardware generated using CAOS, concurrent execution of maximal set of actions in each clock cycle reduces the latency (number of clock cycles) of the design at the cost of increase in its peak power, which is defined as the maximum instantaneous power (due to switching activity) during one clock cycle. In Chapter 5, various heuristics targeting the minimization of peak power in designs generated...
Chapter 8 presents an algorithm for peak power reduction of designs generated using CAOS. The proposed algorithm exploits the fact that for a CAOS-based design, disabling appropriate actions in a clock cycle for reducing its peak power should not alter the functional behavior of the design. This is because for well-written CAOS designs, re-scheduling of the actions of a design for reducing its peak...
In the past, high-level synthesis from CAOS has been shown to produce designs optimized for area and latency. However, not much work had been done in the area of synthesis of low-power hardware designs from CAOS and their verification. This book focuses on solving the problems of generation of power-optimized hardware using CAOS and verification of the synthesized low-power hardware. Power...
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