Hardware implementations generated from CAOS can exploit the parallelism germane in the computation and execute maximal set of actions concurrently in order to reduce the latency of the design. The concurrent execution of actions may result in high peak power and dynamic power consumption in the hardware generated from such specifications. Peak power becomes an issue if large number of actions are executed in the same clock cycle. This is undesirable due to packaging, cooling, and reliability considerations. Furthermore, maximal set of actions executing in each clock cycle implies that more hardware units are working in parallel and result in high switching activity in such designs. This leads to high dynamic power consumption which increases the heat dissipation of the system and limits its battery life. Therefore, in designs generated from CAOS, strategies targeting the reduction of these power consuming activities are required [94] . In this chapter, we formulate the problems of power-optimal synthesis from CAOS. We discuss peak power and dynamic power optimization problems related to CAOS and show that both these problems are NP-hard.