The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In a quest for flexibility, receivers for wireless communications are being digitized. Analog filters and variable gain amplifiers (VGA) are exchanged for digital processing at the expense of a very challenging ADC. Wireless interconnectivity in particular, seems a first candidate for a full-digital baseband implementation. Compared to mobile communication, sensitivity and interferer levels are moderate...
This paper describes the systematic design of ΣΔ analog-to-digital converters (ADC), from the top level of abstraction represented by the filters defining signal and noise transfer functions, passing through the architecture-level, where topology-related performance is calculated and simulated, and finally down to circuit parameters. The systematic approach allows the evaluation of different loop...
A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3...
Modern sensing applications often require high resolution conversion without compromising power consumption. In this Chapter, the maximum out-of-band quantization noise in deltasigma converters is shown to play a key role in optimizing the performance of low power and high resolution delta-sigma analog-to-digital converters (ADCs). Two design examples will be highlighted that illustrate the use of...
Moving into ultra-deep-submicron CMOS technologies, the design of Σ-Δ ADCs faces more challenges. Among them important ones are the restriction from the decreased supply voltage, the higher distortion and degraded device characteristics. The reduced supply voltage decreases the signal swing and lower noise floor is required to maintain the same signal-to-noise ratio. On the other hand, some advantages...
DSP-based FM receivers should be designed paying special attention to the implementation of the A/D converter. This paper overviews the available solutions for these systems by addressing advantages and drawbacks. Large emphasis is given to an implemented bandpass multibit ΣA modulator, deriving its specifications from system requirements, and motivating each design option. Experimental results of...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.