Moving into ultra-deep-submicron CMOS technologies, the design of Σ-Δ ADCs faces more challenges. Among them important ones are the restriction from the decreased supply voltage, the higher distortion and degraded device characteristics. The reduced supply voltage decreases the signal swing and lower noise floor is required to maintain the same signal-to-noise ratio. On the other hand, some advantages are gained. Important ones are the reduced threshold voltage of the transistor and lower power consumption of the digital circuits. In this paper, low-power low-voltage Σ-Δ ADC design strategies are introduced and design techniques in ultra-deep-submicron CMOS technologies are presented. As an example, a 1 V, 20 kHz, 88 dB, 140 µW Σ-Δ modulator design in a 90 nm CMOS technology is presented.