This paper describes the systematic design of ΣΔ analog-to-digital converters (ADC), from the top level of abstraction represented by the filters defining signal and noise transfer functions, passing through the architecture-level, where topology-related performance is calculated and simulated, and finally down to circuit parameters. The systematic approach allows the evaluation of different loop filters and quantizer resolutions, mapped on single-loop or cascaded topologies with both discrete- and continuous-time loop filters.