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Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the...
High resolution ADCs employing histogram test for linearity measurement suffer from high test time. This test time is an important factor in determining the overall cost of the ADC. While alternate test methods for linearity checks in the presence of static errors have been proposed, no low cost test method for the detection of dynamic errors has been reported so far. This paper analyzes dynamic errors...
Solid-state drives (SSDs) based on NAND flash memories provide an attractive storage solution as they are faster and less power hungry than traditional hard-disc drives (HDDs). Aggressive storage density improvements in flash memories enabled reductions of the cost per gigabit but also caused reliability degradations. A recent large-scale study revealed that the uncorrectable bit error rates (UBER)...
To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX...
This paper presents a built-in self-test (BIST) system for Low-Dropout Regulators (LDO). Since the LDO is a closed-loop system, stability is a very important but oft-untested parameter for embedded LDOs. The proposed BIST system can measure stability-related parameters by performing cross correlation between an input pattern mimicking noise in the form of Pseudo Random Binary Sequence (PRBS) and the...
This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes...
A test reordering algorithm is presented to improve the results of scan chain diagnosis when a limited amount of fail data is collected by the tester. Tests are reordered based on information derived by applying an enhanced defect diagnosis procedure to the faulty units with scan defects. Tests that are found important for diagnosis of more faulty units are placed earlier in the test set based on...
This paper proposes a fast-Fourier-transform-based jitter separation and model-based bit-error-rate (BER) curve estimation technique for analyzing asymmetric total jitter distributions. The proposed method assumes asymmetric deterministic jitter models which have distributions denoted by even and odd functions. It separates deterministic jitter and random jitter by identifying the model parameters...
Advances in both semiconductor and automotive industry are today enabling the next generation of vehicles with significant electronics content than ever before. Consumers can now avail vehicle offerings in the form of Electric and Hybrid Electric Vehicles (EV/HEV) that have improved fuel efficiency, provide enhanced driver-passenger comfort and experience through Advance Driver Assistance Systems...
Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
There has been a growing trend in recent years to outsource various aspects of the semiconductor design and manufacturing flow to different parties spread across the globe. Such outsourcing increases the risk of adversaries adding malicious logic, referred to as hardware Trojans, to the original design. In this paper, we introduce a run-time hardware Trojan detection method for microprocessor cores...
This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity...
Prognostic diagnosis is desirable for commercial core router systems to ensure early failure prediction and fast error recovery. The effectiveness of prognostic diagnosis depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect “outliers” when the statistical properties of the monitored data change significantly...
In this paper, we present CORT, a factored concolic execution based methodology for high-level functional test generation. Our test generation effort is visualized as the systematic unraveling of the control-flow response of the design over multiple explorations. We begin by transforming the Register Transfer Level (RTL) source for the design into a high-performance C++ compiled functional simulator...
This paper presents a methodology for reducing functional test time in subthreshold SoCs targeting ultra-low power (ULP) internet-of-things (IoT) devices. Due to their low operating speed and voltage, subthreshold SoCs require significantly longer time to test than traditional SoCs. The proposed method models trans-threshold correlations to allow high voltage, high speed testing while accurately predicting...
A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes.
Multilayer (3D) integrated circuit technology (3D chip technology) provides an attractive alternative to conventional circuit scaling methods, which rely solely on continued shrinking of device dimension. Chip stacking, through the use of through silicon vias (TSVs) and micro ball grid arrays or copper pillars, allows increasing chip complexity in a node independent way. 3D chip technology also opens...
DRAM is a crucial component in computing systems, and is expected to be even more important as data-intensive applications become more prominent. A key challenge in advancing DRAM technology is the growing cost of refresh operations, which can impose a large impact on the energy efficiency of DRAM modules. Existing refresh mitigation techniques all require hardware modifications, which may be undesirable...
Analog-to-Digital Converters (ADCs) are becoming increasingly common to be involved in most systems in Integrated Circuits (ICs). Thanks to the rapid growth of modern semiconductor technology, the performance of the data converters becomes better and better. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually better performance ADCs. The conventional...
A contemporary high-performance system board is a complex 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all of the above not contributing to the ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in the case of now-ubiquitous DDR3 memories. Today, data transmission...
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