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A surface layer formation by Cs+ bombardment was observed during ultra-thin oxynitride gate dielectrics depth profiling. A significant thickness change relative to ultra-thin layer of oxynitride was noticed when testing a bombarded sample after a period of time. Cs, O and N depth profiles were examined by Dynamic Secondary Ion Mass Spectrometry (DSIMS). The bombarded sample and new sample were investigated...
The case study is focus on one of the assembly defect which is invisible during 1st level for analysis. Root-cause finding involved assessment until die level analysis.
This paper discussed the applications of electron energy loss spectroscopy (EELS) for element characterization in semiconductor manufacturing. The first experiment compared the ability of element chemical states analysis between EELS and X-ray photoelectron spectroscopy (XPS). Some phase change random access memory (PcRAM) product suffered TiN connection electrode failure. EELS and XPS were used separately...
Gallium arsenide (GaAs) is an excellent choice of high power amplifier (PA) because it has high electron mobility, linearity, breakdown voltage, base resistance and base loss of m semi-insulating substrates. This paper introduces the internal circuit of power amplifier chip, ESD failure analysis of GaAs MMIC-based power amplifier, performance assessment of GaAs chip and presents a protection design...
Organic thin film transistors with indacenodithiophene — benzothiadiazole (C16IDT-BT) as the semiconducting layer was fabricated to investigate the effect of temperature on the charge carrier mobility. To offer guidelines for optimal working conditions, the temperature range was chosen from 300 K to 460 K. Results showed that the hole mobility improved as the temperature increased until a certain...
Reliability of Superjunction (SJ) MOSFET is closely related to its manufacturing process. Experiments are carried out to investigate the electrical characteristics in high temperature of SJ MOSFET produced by deep trench filling technology. Filling holes are confirmed to be responsible for the performance deterioration in high temperature and the mechanism has been analyzed thoroughly.
A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under...
The large difference between TLP (Transmission Line Pulse) and HBM (Human Body Model) test results of a power NMOS have been analysed using experimental tests as well as physical FA (Failure Analysis). A phenomenological explanation has been provided to account for the negative (positive) voltage surge that occurs during HBM positive (negative) zap on drain due to inductance of the bonding wire. Finally,...
According to previous work about PESD optimization [1], there are some potential risks such as low breakdown voltage (VBD) and low holding voltage (Vh) can be improved for power-rail ESD application. Through drain region design with P-type concentration engineering, the enclosed P-Well in Deep N-Well (EW) in drain region was proposed with high ESD performance (HBM>8kV) and good turn-on efficiency...
In this paper, a method to detect shorts at the gates of the storage node of a 6T SRAM bit cell via atomic force probing (AFP) at the Via 1 level is discussed. This method is useful for the preservation of physical evidence as well as to ease the probing operation due to the lower density and larger separations of vias compared to contacts. One particular case of single bit failure is documented,...
In this study, we perform a top gate field effect transistor by using the integration of novel materials such as graphene as active channel and fluorinated graphene as dielectrics on flexible Polyethylene terephthalate (PET) substrate. These device shows high carrier mobility (∼969 cm2/v.s) at a drain bias of +0.5V. It shows good mechanical flexibility and electrical stability after bending measurement...
RF Power amplifier often demands Zero-defect in application. However, it sees non-uniform stress during application. The time depend stress level depends on the input signals. This paper presents a way to predict the gate oxide lifetime, not only for the intrinsic oxide breakdown, but also for the extrinsic oxide breakdown. An appropriate gate oxide screening condition would enable the desired quality...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
This study investigates the bias temperature instability in high-k/metal-gate pMOSFETs with a TiN barrier layer sandwiched between the metal gate electrode and HfO2 dielectric and for reliability improvement of such devices. The experimental results clearly demonstrated that the diffusion mechanism of oxygen and nitrogen resulting from the post metallization treatment was the root cause of bias temperature...
In this study, impact of traps located at SiO2/Si interface on the time-dependent dielectric breakdown (TDDB) lifetime is investigated by modeling the Weibull distribution in high-k (HK) dielectric stacks. The results show that the interface traps will cause the distortion of Weibull slope of TDDB lifetime, decreasing the growing rate of the probability of breakdown after a long time.
The three-dimensional (3-D) NAND flash memory technology has been considered as a promising candidate for future memory solutions, because it overcomes the scaling limitation and reliability issues faced by conventional planar memory. Even though 3-D NAND flash memory structures have many merits, self-heating effect is aggravated seriously due to the poor thermal conductivity of some of the materials...
With process technology development and circuit density rapidly increases, shrinkage of semiconductor device geometries has become extremely difficult to effectively analyze defect. Therefore, an exactness failure analysis process flow and technique need to be considered in order to analyze the failure mechanism, especially complex failure analysis such as failure of open/floating signal net in logic...
In this paper, we reported a EVB Burn In (B/I) failed case of our ABCD part and led to the finding of VIA process fabrication issue with TiN film process marginal issue. This EVB B/I failed case was carried out by electrical failure analysis (EFA) and physical failure analysis (PFA) using FIB X-section and TEM. This paper also demonstrated different EFA technology, which included curve tracer analysis,...
The clamped inductive turn-off failure of Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multi-finger layout pattern is investigated in this paper. Firstly, the measurements of device failure under clamped inductive turn-off are discussed. Secondly, simulations are carried out to reproduce the failure by using Sentaurus TCAD. It is found that the failure origins from...
In this paper, a new and simple method named Weibull criterion is proposed to identify whether metastable states occur in single random telegraph noise (RTN), which has been verified by both simulation and experiment results. It is helpful for comprehensive understanding of trap properties and providing a direct evidence of oxide traps with multiple states.
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