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Recently, most of researchers focus on low-power design for monitoring, and controlling different smart platforms. Generating reference voltages for power conditioning of these systems is one of the main design challenges of these systems. Therefore, bandgap reference (BGR) is required for providing a temperature, and supply independent reference voltage. This paper presents a CMOS lowvoltageself-startup...
The microbial fuel cells (MFCs) are emerging energy harvesters that are promising for the autonomous supply of seafloors remote sensors. Regarding the low voltage and power level delivered by MFC an electrical interface is required to condition the sensors needs. The flyback in discontinuous conduction mode appears to be the best candidate to extract the maximum power delivered by the MFC, to electrically...
Development of tactile sensing systems is motivated by the possibility of application in many domains such as robotics, prosthetics, and industrial automation. This paper provides a functionality assessment of an interface electronic circuit prototype for tactile sensing systems. The circuits are based on the DDC112U and an FPGA Xilinx Spartan-6. An experimental setup is carried out to measure the...
In most robotic and biomedical applications, the interest for real-time embedded systems with tactile ability has been growing. For example in prosthetics, a dedicated portable system is needed for developing wearable devices. The main challenges for such systems are low latency, low power consumption and reduced hardware complexity. In order to improve hardware efficiency and reduce power consumption,...
FPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low-medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded...
Convolutional Neural Networks (CNNs) allow fast and precise image recognition. Nowadays this capability is highly requested in the embedded system domain for video processing applications such as video surveillance and homeland security. Moreover, with the increasing requirement of portable and ubiquitous processing, power consumption is a key issue to be accounted for.In this paper, we present an...
This work presents a rad-hard by design (RHBD) 10-bit 1MHz SAR ADC for space applications. The goal is to design a radiation tolerant SAR ADC by using radiationhardened by design (RHBD) techniques both at circuit and layout levels. The various influences of the radiation which could degraded the circuits in harsh and radiation environments have been taken into account by the design. A conventional...
A low-power frequency-synthesizer is proposed using a charge-pump PLL architecture based on the novel nanowire SGFET technology. The output frequency of the system is 10.3125 GHz, synthesized from a reference input of 156.25 MHz. The design utilizes a phase-frequency detector, a charge-pump, a 2nd order passive loop-filter, a current-starved ring voltage-controlled oscillator, and a frequency divider...
This paper proposes a redundant sense amplifier for radiation-hardened SRAMs, based on a latched cross-coupled topology. First, the most common issues related to SRAMs reliability and performances in radiation environments are discussed. Then, after an analytical study on the transient effects induced by radiations, based on a systematic design flow, a novel redundant sensing scheme is presented and...
The size of counterfeiting activities is increasing day by day. These activities are encountered especially in electronics market. In this paper, a countermeasure against counterfeiting on intellectual properties (IP) on Field-Programmable Gate Arrays (FPGA) is proposed. FPGA vendors provide bitstream ciphering as an IP security solution such as battery-backed or non-volatile FPGAs. However, these...
This paper presents an analytical model of a tapped shift-register based delay generator, which is currently implemented in the High Momentum Particle Identification Detector (HMPID) at CERN and will be upgraded in the coming years. This work aims to verify whether this delay generator can be optimized to provide a delay range of 525 ns with a resolution of 1 ns. In particular, this paper studies...
This paper presents the feasibility study of a low-power 5-bit synchronous current-mode SAR ADC primarily targeted for ultra high speed applications. The circuit uses a voltage-current converter at the front end and a current steering DAC. The discrete analog output is digitized by a latch and a standard SAR logic in feedback to process the information by using a binary search algorithm. The proposed...
Fine-grained power management of largely-integrated manycore systems is becoming mainstream in order to deal with tight power budgets. As a result, some level of asynchrony is becoming inevitable for efficient system-level operation. Asynchronous interconnection networks naturally provide such asynchrony, however their wide industrial uptake depends on the capability to overcome two fundamental barriers:...
This paper presents an overview of a family of asynchronous arbitration primitives designed to increase the resilience and efficiency of the new generation of circuits and systems. We cover primitives for synchronisation and decision-making with an emphasis on interfacing analogue and digital worlds, sampling of non-persistent signals, and efficient handling of correlated sensor events.
Asynchronous circuit design has been introduced many decades ago, however until now with the limited industry application. This paper summarizes the basic asynchronous principles and techniques, as well as the latest developments as well as the outlook.
Real-time systems need a time-predictable computing platform. Computation, communication, and access to shared resources needs to be time-predictable. We use time division multiplexing to statically schedule all computation and communication resources, such as access to main memory or message passing over a network-on-chip. We use time-driven communication over an asynchronous network-on-chip to enable...
This paper presents a perceptron circuit which can be implemented into sensor analog front-end consistent with neural network-based machine learning. We introduce a DAC-based multiplier in the perceptron circuit, where the DAC is used as a programmable resistor. Compared with a traditional transconductor-based multiplier, the precision of our multiplier is formulated only by the digital codes, and...
A clock recovery gated phase locked loop (GPLL) for periodically missing input signals and 100% amplitude shift keying modulation is presented. The On-Off keying scheme leads to long periods without an RF signal to extract. This poses special requirements that can be met by using gated PFDs. The power control technique used in this implant periodically shorts the receiving coil, thus limiting the...
Personalized drug dosage is crucial to ensure op- timal benefit in patient’s treatments. Therefore, many efforts are done in developing integrated, low-cost and portable point- of-care sensing systems able to continuously monitor the drug concentration. To satisfy this request, a portable multi-channel system is here presented and validated. The system is able to run different electrochemical techniques...
This paper describes a novel readout integrated circuit (ROIC) for a photoresistive image sensor array incorporating Wheatstone bridge configuration with a variable-gain switched-capacitor amplifier. A 12-bit R-2R ladder digital-to-analog converter (DAC) and a variable-gain switched capacitor amplifier are used for on-chip offset and gain calibration. The bias voltage of the bridge is supplied by...
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