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In this paper the noise behavior of a novel Avalanche Ion Sensitive Field Effect Transistor (A-ISFET) is presented. The A-ISFET is an ion sensitive field effect transistor that can inherently deliver high sensitivity through a multiplication factor, M, similar to an avalanche photodiode, where they are used when the input signal is very weak. A physical model for both intrinsic and extrinsic noise...
As seen in stream data processing, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M,N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers (MUXs). However, the number of required MUXs increases too much as the input/output byte lengths increase...
This paper presents a technique that utilizes comparator timing information to accelerate successive approximation register (SAR) analog-to-digital converter (ADC) conversion process. With the scaling down of power supply voltage, the comparator delay is exponentially increasing. Thus, more information can be potentially extracted from the comparator transient response. In the proposed approach, the...
Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize...
This paper presents a 4.8 V tolerant circuit for reliably switching a startup load between a main power supply and a battery power supply. The circuit automatically switches the main power supply over to the battery in case the main line has been interrupted. The circuit includes a pair of back-to-back switch transistors for isolating the load from each power supply, a bias circuit for controlling...
With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant...
This paper presents compressive image sensor techniques based on sparse measurement matrices. Existing compressive sensing (CS) CMOS image sensors use dense random measurement matrices, which face the challenges of excessive hardware overhead and large signal swing requirement. The sparse measurement matrices proposed in this paper dramatically simplify the circuit implementation and relax the signal...
We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure...
We show the first camera based (privacy-preserving) indoor mobile positioning system, CaPSuLe, which does not involve any communication (or data transfer) with any other device or the cloud. The algorithm only needs 78.9MB of memory and can localize a mobile device with 92.11% accuracy. Furthermore this is done in 1.92 seconds of on-device computation consuming 3.77 Joules of energy, as evaluated...
Energy and power consumption are major limitations to continued scaling of computing systems. Inexactness where the quality of the solution can be traded for energy savings has been proposed as a counterintuitive approach to overcoming those limitation. However, in the past, inexactness has been necessitated the need for highly customized or specialized hardware. In order to move away from customization,...
In this paper, we introduce low-power and real-time intelligent SoCs aimed at smart machines. To implement intelligent functions under low-power consumption, machine learning methods are tightly integrated with the traditional algorithms. At first, an object recognition processor (ORP) accelerating scale-invariant feature transform (SIFT) is presented with a visual attention based on convolutional...
Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA...
Spin Transfer Torque (STT) is a promising technology for storage in which the information is stored in the form of magnetic orientation of a Magnetic Tunnel Junction (MTJ) rather than electric charge. Besides memory applications, this technology is promising for non-volatile reconfigurable logic design. The major challenge in realizing this technology is the power and performance overhead associated...
Quantum-well infrared photodetectors (QWIPs) have become research focus in recent years due to its many inherent properties. However, the measurement of internal parameters is very difficult; instead, computer simulation and device modeling provide a better way to analyze quantum structure devices. In order to solve this issue, the electronics performance and the optical performance of a QWIP fabricated...
This paper discusses the performance impact of interconnect parasitic resistance and capacitance for SoC (System on Chip) design beyond 10-nm FinFET technology. As technology scaling advances, the impact of BEOL (Back End of Line) is recognized as one influencer on operating performance. Using typical logic standard cells, sensitivity analysis by DOE (Design of Experiments) shows that the parasitic...
This paper presents a low power ΣΔ CMOS modulator with op-amps operating in subthreshold region for processing bio-signals. In order to reduce a power consumption of the proposed fourth order ΣΔ CMOS modulator, two opamps for implementation of integrators are designed to be operating in subthreshold region. For furthermore power reduction, the first two integrators are re-utilized with switches and...
Memory systems like Static Random Access Memories (SRAM) and Non Volatile Memories (NVM) thrive on area and power efficient designs. This paper presents a novel and a power proficient design of a Dual Functionality Read-Write (DFR-W) driver for SRAM sub-system. This design is integrated with a memory sub-system with an operating frequency of 1GHz in CMOS 65nm technology. It is then compared with a...
This paper presents a novel (3.3 v) mobile compatible RF MEMS switch operating in the RF range (DC-6 GHz) in order to be integrated with a reconfigurable microstrip antenna. The switch is a metal series type and utilises dual supply lines controlling 4 electrostatic actuation electrodes with two cantilevers acting vice versa, the design eliminates the stiction problems, suffers low stress levels and...
Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a...
Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2× code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length...
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