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Carbon-based nonvolatile resistive memories are an emerging technology. Switching endurance remains a challenge in carbon memories based on tetrahedral amorphous carbon (ta-C). One way to counter this is by oxygenation to increase the repeatability of reversible switching. Here, we overview the current status of carbon memories. We then present a comparative study of oxygen-free and oxygenated carbon-based...
We propose a comparative analysis for Ge2Sb2Te5 (GST) and Ge-rich GST based Phase-Change Memory (PCM) devices in terms of program/read disturbs robustness. We present the characterization of the intrinsic drift of the materials, the investigation of the devices response to electrical stress and, finally, the study of the PCM cell behavior in extreme disturb conditions. A higher immunity for Ge-rich...
In this paper the memory performances of the TiN/HfO2/Ti/TiN and TiN/Ta2O5/TaOx/TiN memory stacks are compared. First, the bipolar switching parameters and the effect of the compliance current on the memory window and endurance are investigated. Then, the endurance and data retention properties are compared at a given operating current (100µA). Ta2O5 based memory stack exhibits a better memory window...
The resistive switching behavior in different HfO2/TiO2 nano crossbar structures of 100 x 100 nm² size is analyzed by means of DC voltage sweeps. The devices fabricated from 3 nm thin ALD layers of HfO2 and TiO2 sandwiched between Pt and Hf or Ti electrodes show VCM-type bipolar resistive switching after electroforming. For increased compliance current (cc) during set from 50 µA to 800 µA, the set...
Factors affecting SET-disturb failure time (τf) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of...
STT-MRAM are foreseen as the best contender for DRAM replacement. STT-MRAM could also be used for SRAM applications if switching time below 1ns could be realized in a reliable way. In this study, we demonstrate that sub-ns switching with final state determined by the current polarity through the stack can be achieved in STT-MRAM cells comprising two spinpolarizing layers having orthogonal magnetic...
A systematic study of dominant program-disturb mechanisms in advanced embedded split-gate SuperFlash memory across ambient temperature ranging from -45C to 175C is presented. At low temperatures program disturb is initiated by trap-assisted band-to-band tunneling in the split-gate channel area and/or trap-assisted tunneling via thin select gate oxide and at high temperatures - by surface generation...
Symmetrical (Pt) electroded undoped (Pt/a-VOx/Pt) and Cr-doped amorphous Vanadium Oxide (Pt/a-V1-yCryOx/Pt) devices were fabricated and electrically analyzed. Both devices show reproducible and symmetrical threshold switching after an initial forming step. However, the kind of threshold switching was basically different. For the undoped VOx, threshold switching was identified as a low TC, VO2-type...
In this paper we propose a novel oxide-based RRAM stack using hygroscopic oxide, doped Gd-O, as resistive switching layer integrated in a CMOS friendly flow. Operating at 50µA, the stack features large resistive window (>x100) and superior endurance lifetime (10^12) which is to our knowledge the record lifetime for CMOS compatible RRAM devices. Detailed benchmarking between conventional oxide-based...
In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then...
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write...
A totally analytic compact model of bipolar switching in oxide based resistive memory is reported. Analytical expressions reproducing the switching in the case of ramp voltage and short voltage pulses without any iterative procedure are given. The model results are compared to experimental data and to a numerical model containing the same physical basis.
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