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The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The...
In this paper a gradual investigation of a particular Hall sensor in SOI (“Silicon-On-Insulator”) technology is presented. The most important parameters of a specific Hall cell, based on SOI structure, are evaluated through three-dimensional physical simulations. The fact that the depth of the active silicon layer in SOI integration process is much smaller than in a regular CMOS is immediately reflected...
This paper presents a semi-empirical model of the mobile charge in the channel of a junctionless dual-gate MOSFET. Its accuracy has been demonstrated to be better than 1% of the total depletion charge for a wide range of channel thickness and substrate doping values.
This paper describes the boost converter analyses using electrothermal average models. The form of electrothermal average models of the diode — transistor switch and the inductor dedicated for SPICE is shown. The usefulness of the presented models to calculate the characteristics of the boost converters is shown on the example of a boost converter containing the inductor with the ferrite core. The...
Noise canceling techniques have been successfully applied to the design of modern multi-band RF-CMOS inductor-less receivers. However, low voltage supply requirements are imposing new design challenges which are pushing the operation of the MOS transistor into moderate or weak inversion, making the setup of closed sizing expressions a difficult task. This paper presents a Si2 OpenAccess based circuit...
High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model...
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