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This paper presents a high-resolution ΔΣ modulator which is capable of operation under supply voltage as low as 250mV. A novel subthreshold inverter-based OTA is proposed and exploited in the switched-capacitor (SC) integrators, permitting a satisfied noise-shaping performance in the 4th-order feed-forward topology. With each stage's coefficient optimized, the integrators' internal swings and the...
This paper presents a Transformer-Coupled Quadrature VCO (TC-QVCO) designed to achieve low-noise performance at millimeter-wave. The VCO core is implemented combining the tuned-input tuned-output (TITO) oscillator and the Colpitts oscillator, while the coupling is realized by means of transformers, resulting in low noise and accurate quadrature phases. Designed in a 40 nm CMOS process, the TC-QVCO...
This paper presents an original mmW frequency multiplier that provides a 58.32 GHz to 62.64 GHz LO starting from a much lower and fixed frequency of 2.16 GHz. It is composed of a pulsed VCO, which generates equally spaced harmonics in the 60 GHz band, and an injection locked oscillator (ILO) that selects the harmonic of interest. The CMOS 40nm circuit consumes 32 mW and occupies only 0.07 mm2. This...
We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the...
A 16 Gb/s receiver implemented in 22 nm SOI CMOS technology is reported. The analog frontend accepts a rail-to-rail input common-mode imposed from the transmitter side. It consists of a baseline wander compensated passive linear equalizer that AC-couples the received signal to the subsequent active CTLE with a regulated common-mode level. The programmable passive linear equalizer features a frequency...
A half-rate decision feedback equalizer (DFE) with two infinite impulse response (IIR) filters and one discrete-time tap is presented. The two IIR filters have different time constants to cancel the long tail of the pulse response. The discrete-tap cancels the first post-cursor inter-symbol interference term. The system can operate with a low transmit swing of 150mVpp-diff and 24 dB channel loss at...
This paper presents a 8 Gbps high jitter tolerance (JTOL) corner-frequency hybrid CDR that employs blind oversampling phase detector in conjunction with digital proportional integral controller (PIC) for phase/frequency tracking with +/−4000ppm frequency offset compensation over infinite burst. Need of the elasticity buffer has been obviated by using a method of time-varying divider ratios in word-clock...
A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking...
This paper presents a 7-bit 3.2-GHz injection-locked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved...
In this paper, we present a digital equalizer for 16Gb/s backplane I/Os which consumes only 3.5pJ/bit for an 8-tap FFE and 4+4 tap DFE operation. Several design choices were chosen to enable low power consumption at high speed. First, the FFE leverages parallelism to lower the supply voltage, while the DFE runs from a higher supply to close the feedback loop. Second, the FFE uses distributed arithmetic...
This paper presents a low band antenna impedance tuner in 130nm CMOS-SOI technology. It consists of three digitally controlled switched capacitor banks and two off-chip inductors and is intended for use in terminals supporting modern cellular standards like WCDMA and LTE. By using a negative gate bias in the off state, linearity can be improved and maintained. Measurements show an OIP3 exceeding +55dBm...
An electrical-balance duplexer uses series connected step-down transformers to enhance linearity and power handling capability by reducing the voltage swing across nonlinear components. Wideband, dual-notch Tx-to-Rx isolation is demonstrated experimentally with a planar inverted-F antenna. The 0.18µm CMOS prototype achieves >50dB isolation for 220MHz aggregated bandwidth or >40dB dual-notch...
A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS...
A 28 nm CMOS mixed-signal front end is integrated with a multicore baseband processing platform for GSM /EDGE/WCDMA /HSPA /LTE /Multimedia applications. The AFE path includes an enhanced continuous-time ADC that achieves 73 dB SNDR at 9 MHz mode. AFE TX features a push-pull DAC with 13-bit linearity and 8.7 nV/sqrtHz noise density at 30 MHz. The high-fidelity audio playback and capture paths achieve...
A 28 nm 4G/LTE mobile System-on-Chip (SoC) with digitally-assisted analog and analog-assisted digital design techniques is presented. Multicore processors with integrated switching regulators achieve 1.8 GHz and 1.5 GHz speeds for A15 and A7 processors, respectively. The multiphase integrated switching regulator achieves 90% efficiency and up to 8A current capability. PVT monitors enable DVFS and...
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