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A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated...
A design methodology for interstage and output matching networks for wide-band Power Amplifiers for wireless applications is proposed. Leveraging wideband inductively coupled resonators, we apply Norton transformations for impedance matching. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output...
This paper presents a 79GHz variable gain low-noise amplifier (LNA) and power amplifier (PA), both implemented in 28nm CMOS, and measured at temperatures from 27°C to 125°C. The 4-gain steps LNA and the 17dB gain PA are based on a multistage common source neutralized push-pull topology. The LNA achieves a gain of 23.8dB and a noise figure (NF) of 4.9dB, and the PA achieves a maximum power added efficiency...
A CMOS high-sensitivity super-regenerative receiver is proposed for millimeter-wave imaging systems. With quench-control signals, two LC-tank oscillators are coupled in-phase by zero-phase-shifter network in a positive feedback loop. This leads to a high oscillatory amplification and improves the detection sensitivity. The circuit is realized in 65nm CMOS with a core area of 0.06 mm2. Measurements...
Most vision applications such as object recognition and augmented reality require a high resolution image because their performance is heavily dependent on a local feature point like an edge and a corner. Unfortunately, the vulnerability of correct feature detection always exists in vision applications. Moreover, it is hard to increase image resolution because there is the trade-off between the image...
A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted...
A 64-bit dual-core RISC-V processor with vector accelerators has been fabricated in a 45nm SOI process. This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley. In a standard 40nm process, the RISC-V scalar core scores 10% higher in DMIPS/MHz than the Cortex-A5, ARM's comparable single-issue in-order scalar core, and is 49% more...
In this paper the first complete Evolved EDGE transceiver physical layer ASIC supporting receive diversity and soft-output Viterbi equalization is presented. It comprises transmitter and receiver with detector and a decoder with an autonomous incremental redundancy implementation. The ASIC reaches a measured sensitivity of −111.8dBm for single antenna GSM voice channels and achieves the reference...
This paper presents a 5GS/s 8-bit 40-way time-interleaved SAR ADC fabricated in 65nm CMOS. Two-level hierarchical interleaving is employed, resulting in 4 sub-ADCs each operating at 1.25GS/s at the topmost level with front-end track and hold samplers. The sub-ADCs use capacitive C-2C DACs to minimize the input capacitance and area. A novel background timing skew calibration method is used which requires...
This paper presents a sub-ranging 6-way time-interleaved pipelined-SAR ADC that achieves 900MS/s and 9.3 ENOB in 65nm CMOS. The architecture optimization is based on a pipelined-SAR structure that obtains high-speed with an optimized number of channels, thus leading to relaxed calibration with higher efficiency in power and area consumption. The proposed channel-selection-embedded bootstrap performs...
A complementary dynamic single-stage residue amplifier for a pipelined SAR ADC is presented. It re-uses charge typically wasted during the reset phase, and hence improves efficiency by a factor 2× in this block that often dominates the fundamental noise/power trade-off of the ADC. The residue amplifier achieves 90 µVrms input noise for an energy consumption of 1.5 pJ. It is used in a 2-times interleaved...
This paper presents a low-power SAR ADC with a bidirectional single-side (BSS) switching technique. It reduces the DAC reference power and the total number of unit capacitors by 86% and 75% respectively, compared to the conventional SAR switching technique. It also minimizes the DAC switch driving power as it has only 1 single-side switching event every comparison cycle. Unlike the existing monotonic...
This paper describes a combination of a Weaver mixer and an N-path filter for a superheterodyne receiver with a reconfigurable frequency plan. It uses an N-path topology driven with two different frequencies, effectively realizing a frequency shift together with band-pass filtering. To reduce transfers via harmonics other than the fundamental, a harmonic rejection scheme is used. A 28nm FDSOI CMOS...
We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3...
We present a new type of flicker noise, mismatch up-converting active mixer with an odd number of cascode switching pairs that relax the local oscillator (LO) switching speed, which reduces the flicker noise from indirect mechanisms. The high-crossing master LO drivers improve the IIP3 at a 1.2 V supply voltage, and a frequency-reconfigurable LO generator is also presented for multiband operations...
This paper presents a 2.45 GHz wake-up receiver front-end intended for use in sensor networks, and is designed to receive data modulated with on-off-keying. Manufactured in 65 nm CMOS it employs an uncertain IF structure with three-phase passive mixer and high gain amplifier chain. With the modulation frequency response tailored to the detector behavior, it achieves a sensitivity of −88 dBm at BER...
A 250K probing-resilient PUF array with measured 2GHz operation and total energy consumption of 13fJ/bit at 0.9V, 25°C is fabricated in 22nm tri-gate CMOS. Hybrid PUF circuit with integrated load modulation and run-time soft dark-bit mask generation enables identification of unstable PUF bits with 100% accuracy, eliminating the need for multiple voltage/temperature characterization while also reducing...
A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction...
This paper describes the clock distribution and synchronization network for a 64bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40nm CMOS technology and operates at 3.0GHz. The system PLL has a measured rms jitter <1psec and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the...
This paper presents a scalable all-digital power supply noise analyzer with 20GHz sampling bandwidth and 1mV resolution implemented in 32nm CMOS. This averaging-based analyzer measures power supply noise in both the equivalent-time and frequency domain with low-resolution VCO-based samplers. For frequency-domain measurements, it uses digital random phase-noise accumulation to remove correlation between...
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