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A 16-core processor for software-defined radios is realized in 40nm CMOS. Featuring domain-specific kernels, flexible control and multi-scale interconnects, the processor achieves a peak energy efficiency of 13.1GOPS/mW (76fJ/OP) at 415mV, 25MHz, and a peak performance of 1.17TOPS at 1V, 500MHz, showing >2.4× higher energy efficiency than state-of-the-art communication chip multiprocessors, and...
Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and...
For the heterogeneous-structured high bandwidth memory (HBM) DRAM, it is important to guarantee the reliability of TSV connections. An exact TSV current scan and repair method is proposed, that uses similar to the correlated double sampling method. The register-based pre-repair method improves testability. The measurement results for thousands of TSV shows impedance distribution under 0.1 ohm. Methods...
This paper presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC). To reduce the total amount of capacitance and relieve requirement of comparator, we propose a hybrid architecture composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated...
A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise,...
This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]...
This paper presents an ultra-low-power 2-step wake-up receiver for the IEEE 802.15.4g. The receiver is composed of an ultra-low-power energy-detection receiver (EDRX) and an address-detection FSK receiver (ADRX). The ADRX is activated only when the EDRX detects a wakeup packet which minimizes power consumption. Fabricated in a 65 nm CMOS process, the receiver achieves an excellent receiver sensitivity...
We present a power/data telemetry IC with a new data modulation scheme and simultaneous power transfer through a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive power while inducing an instantaneous voltage change at the primary side. Cyclic on-off keying time-encoded symbol mapping of the shorting cycle allows transmission of two data...
A wireless-powered pad-less single-chip dual-band mm-wave passive radio is implemented in 65nm CMOS for applications in sensor networks and wireless tagging. This fully self-sufficient system has no pads or external components (e.g. power supply), and the entire radio is a single 3.7mm × 1.2mm chip. To provide multi-access, and to mitigate interference, it uses two separate mm-wave bands for RX/TX...
A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of a transistor of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, a kind of CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, a 32-bit processor has been fabricated with 350-nm Si/180-nm CAAC oxide semiconductor technology,...
The proposed cross-source energy (CSE) harvesting circuit can accept universal energy sources, including AC and DC sources. The buck-boost conversion of CSE harvesting circuit automatically converts AC or DC input into DC output without being limited by universal input voltage range. CSE harvesting circuit provides dual outputs, a regulated output and a battery charging output, to optimally arrange...
A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of...
A 13.56MHz wireless power transfer system with a 1X/2X reconfigurable resonant regulating (R3) rectifier and wireless power control for biomedical implants is presented. Output voltage regulation is achieved through two mechanisms: the local PWM loop of the secondary side controls the duty cycle of switching the rectifier between the 1X and 2X modes; and to adapt to load and coupling variations, the...
A fourth-order Chebyshev high-pass filter (HPF) that achieves input-referred noise of 3nV/√Hz, MTPR greater than 72dB, and power consumption of less than 81mW with 0.7mm2 area in 28nm CMOS is presented. Area and power reductions are realized via a mixed-signal filter topology.
A 65nm CMOS 4.78mm2 integrated neuromodulation SoC consumes 417µW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250µs/phase, differential current of 150µA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest...
An electrocardiography SoC is integrated into a formfitting textile along with flexible electrodes, battery and antenna. Clinically standard 12-lead ECG is recorded from this “smart shirt.” The data is encrypted and wirelessly transmitted via an on-chip ISM band radio and flexible antenna allowing secure, continuous cardiac monitoring on a smartphone while dissipating less than 1mW.
This paper presents a self-aware processor with energy monitoring circuits that can measure actual energy consumption of the key blocks. The monitors are embedded into on-chip DC/DC converters and generate results within 10% of accuracy with minimal power (<0.1%) and area (<1%) overhead. Our system, which is implemented in 0.18µm technology, is designed to be voltage scalable from 1.8V down...
A cryptographic engine (CE) resistant to local EM-analysis attacks (L-EMAs) is developed. An LC-oscillator-based tamper-access sensor detects a micro EM-probe approach and therefore protects the secret key information. A fully-digital sensor circuit with a reference-free dual-coil sensing scheme and a ring-oscillator-based one-step digital sensor calibration reduces the sensor area overhead to 1.6%...
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter...
A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with...
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