The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a two-step incremental ADC (lADC) using extended counting. In the first step, the lADC is configured as a first-order ΔΣ loop with an input feedforward architecture. In the second step, a two-capacitor SAR-assisted extended counting technique enhances the accuracy. A single active integrator is shared in both steps. Fabricated in 0.18-μm CMOS process, the IADC achieves a peak SNR/SNDR/DR...
This work presents a delta-sigma modulator free in-loop-bandwidth spread-spectrum clock generator. The proposed charge-based discrete-time loop filter with a digital-to-current converter enables wide range spread-spectrum frequency modulation with significantly relaxed PVT sensitivity. A correlated double sampling technique is leveraged to minimize 1/f noise in the proposed discrete-time loop filter...
A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion...
This paper presents an in-loop-bandwidth spread-spectrum clock generation by proposing a linear charge-based discrete-time loop filter. The proposed architecture achieves a power efficient (2.29mA/GHz) spread-spectrum modulation scheme based upon a conventional CP-PLL. This work supports a modulation range of +/−2.7 % of a 700 MHz output frequency with the modulation rate in the range of 10 ∼ 100...
A third-order switched-capacitor low-distortion delta-sigma ADC with shifted loop delays (SLD) is described, and its performance is discussed. It can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the last stage adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and −95...
A hybrid dynamic amplifier is proposed which combines the desirable features of a dynamic amplifier and a class AB amplifier. This technique allows us to achieve a power efficient high resolution pipeline ADC. A proof of concept pipelined ADC in a 0.18 µm CMOS process achieves 74.2 dB SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 mm...
This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers...
A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR...
To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power and complexity. This amplification performance bottleneck has been highlighted in recent years by the disparity...
In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.