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This paper presents a novel framework for implementing portable and scalable data-intensive applications on reconfigurable hardware. Instead of using expensive “reconfigurable supercomputers”, we focus our work on standard PCs and PCI-Express extension cards featuring Field-Programmable Gate Arrays (FPGAs) and memory. In our framework, we exploit task-level parallelism by manually partitioning applications...
The paper presents a novel hardware block that can be used for simultaneous generation of random bits and PUF responses. The new element called Universal Transition Effect Ring Oscillator (UTERO) is based on the TERO loop presented at CHES 2010. The PUF response bit corresponds to the output value of the TERO loop that converges to a state determined by the manufacturing process. The random bit is...
FPGAs enable NoC architecture experimentation, although to be effective they need to be supported by tools and frameworks for construction of the NoC and effective software programming of the NoC. In this paper, we focus upon effective programming of the NoC using Java, complementing previous work which proposes the Blueshell framework for NoC generation for FPGAs. The approach taken is called Network-Chi,...
In recent years two main platforms emerged as powerful key players in the domain of parallel computing: GPUs and FPGAs. Many researches investigate interaction and benefits of coupling them with a general purpose processor (CPU), but very few, and only very recently, integrate the two in the same computational system. Even less research are focusing on direct interaction of the two platforms [1]....
Side-channel analysis is one of the most efficient techniques available to an attacker to break the security of a cryptographic device. Started as monitoring of computation time or power, it has evolved into considering several other possible information leakage sources, such as electromagnetic (EM) emissions. EM waves can be a very attractive means to attack a cryptographic implementation: they are...
One of the pitfalls of FPGA design is the relatively long implementation time when compared to alternative architectures, such as CPU, GPU or DSP. This time can be greatly reduced however by using tools that can generate hardware systems in the form of a hardware description language (HDL) from high-level languages such as C, C++, or Python. Such implementations can be optimized by applying special...
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