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A bidirectional SSTL I/O which utilizes an active-biasing technique to achieve enhanced ESD resilience is presented. During an ESD event, each vulnerable transistor has an appropriate bias applied to minimize the peak voltage across gate oxide and drain-source regions. Active-bias control circuits can be substituted for secondary protection to improve circuit performance and ESD reliability.
In this paper two new types of single domain CDM failures in a 90nm flash CMOS-technology are reported where sender and receiver of the failed devices are located in the same power domain. The aspects that make these intra-domain signals susceptible to CDM failure are discussed and an automated method for detection of critical constructions is presented as well as proven circuit improvement
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