The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Today, the need for high performance computation method for align biological sequence has increased due to exponential growth of biological sequence databases. Therefore, this paper is an attempt to study and investigate the potential of graph theory algorithm approach for optimizing the alignment process of DNA sequences towards determines the region of common between two or more DNA sequences. This...
Wave-pipelining enables a digital circuit to be operated at higher frequency. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of clock and clock skew between the I/O registers of wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined...
In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wave-pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks...
In this paper we propose a technique for software-implementation of an UART (Universal-Asynchronous-Receive-Transmit) with the goal of getting a customizable UART-core which can be used as a module in implementing a bigger system irrespective of ones choice of implementation platform. Here we have written the core in VHDL (VHSIC hardware description language), implemented using XILINX ISE 10.1 Design...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.