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It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a multi-level cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of...
Phase Change Memory (PCM) recently has emerged as a promising memory technology. However it suffers from limited write endurance. Recent studies have shown that the lifetime of PCM cells heavily depends on the RESET energy. Typically, larger than optimal RESET current is employed to accommodate process variation. This leads to over-programming of cells, and dramatically-shortened lifetime. This paper...
This paper demonstrates single-stage boost rectification for electromagnetic energy harvesters down to approximately 100 μW using practical low-power techniques. The circuits exploit the inductance of the generator, and operate without a discrete inductor, which facilitates integration. Experimental results demonstrate the importance of switching device selection, and the compound effect of the duty...
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