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With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools....
Test, validation and characterization of high-speed circuits is a becoming a complex issue due to increase in circuit marginality, higher fallout, and more complex test solutions. The issue is compounded by the complex interactions between packaged components; interconnect design and customer board designs. This session will address the challenges in characterizing high-speed circuits including PLLs...
The special session covers the following: programmability based approach to post-silicon debug and rectification; an EDA tool chain for soft-error tolerant VLSI design; accurate and efficient SoC field test for failure prediction.
Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans...
Summary form only given. In the industry today, testing packaged chips achieves the outgoing DPPM (defective parts per million) requirements. Usually, functional and structural test patterns are used at wafer sort, followed by functional/structural testing with packaged parts, and then by functional system level testing, each subsequent stage significantly more expensive than the previous one. By...
Over the past decade, the resistive memory device known as RRAM has been studied extensively in many ways, and many of its problems have been identified, discussed, and some solved. It is time to move from material, process, and device to circuit design and yield, in order to commercialize RRAM. However, as we move from resistive device to memory circuit, new problems do appear, partly because the...
Today's electronic systems and those envisioned for the near future exploit significant integration of devices on a chip with incredibly shrinking device/interconnect geometries. Such systems operate very close to their power/performance margins to achieve maximum profitability. The increase in the design complexity of such systems that now include digital and analog components, coupled with the race...
Hold timing closure and scan power are major concerns for any design. Hold closure for scan shift operation generally causes addition of buffers in the data path between flip-flops. This results in increased gate count that will toggle during the functional mode of operation thereby resulting in an increase in functional power. Scan operation also causes higher switching activity due to high toggling...
On-chip linear decompression-based schemes have been widely adopted by industrial circuits nowadays to effectively reduce the ever increasing test data volume and test time. Though they can easily achieve relatively high compression ratio, there is a bound of effective compression ratio for these compression schemes. Prior work tried to address this problem by trying different compression architectures...
The goal of this hot topic session is to discuss this cutting-edge topic that is being researched by several teams in both academia and industry, and debate which is the best approach for sub-65nm silicon designs. The point of debate will be what embedded circuits make the most sense (aging, enablement of more aggressive design, characterization, diagnosis, debug, etc.).
In this hot topic session, we are including three talks that cover design of reliable, emerging memories, with emphasis on 3D memories, DRAM and non-volatile memories. We will also introduce a new class of memory, the Storage Class Memory (SCM), and discuss its reliability issues.
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