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The paper proposes a new parallel hardware architecture for a connected component tree computation. It is an original implementation of the recently published parallel algorithm based on building of a 1D tree for each individual image line and their progressive merging. The image is divided into independent partitions which are processed concurrently. Nevertheless, merging of these partitions requires...
The newest generation of sequencing instruments, such as Illumina/Solexa Genome Analyzer and ABI SOLiD, can generate hundreds of millions of short DNA “reads” from a single run. These reads must be matched against a reference genome to identify their original location. Due to sequencing errors or variations in the sequenced genome, the matching procedure must allow a variable but limited number of...
This paper presents the design and FPGA implementation of a 2nd order all-digital Adaptive Delta Sigma (ΔΣ) modulator with one bit quantization. It has a modulator stage and an adaptation stage. The adaptation stage produces a feedback signal that tracks the input signal and is subtracted from it. This difference signal is in a controlled and reduced range. It is given to the input of the modulator...
The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper...
This paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution video (640 × 480 pixels) at 56 frames per second (fps). Our...
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