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A quantitative analysis of the effects causing the maximum cutoff frequency reduction as horizontal device dimensions are downscaled is carried out. Simple analytical expressions describing the geometry dependence of the maximum cutoff frequency fT and forward transit time are derived, and verified with numerical simulations. These expressions suggest a simple method to extract the values of the maximum...
Hot-carrier (HC) degradation of analog operation parameters has been investigated by stressing LDD-n-MOSFETs with channel lengths of 1.0 - 5.0 ??m. A model has been developed to clarify the different mechanisms leading to degradation of the differential drain output resistance. Experimental evidence is given to check the model. Finally, possible consequences in the circuit environment are discussed.
Using only a few numerical calculations, we give the analytical current-voltage and charge-voltage characteristics valid for any PBT. The highest unity current gain frequency (fT) corresponding to the current technology is on the order of 30 GHz ; nevertheless, the oscillation frequency can be higher than 100 GHz.
Permeable base transistors (PBT) with metal gates and pn-junction gates have been fabricated with conventional device technology. Measurement results compared with simulations are presented. Although the structures are not optimised, cutoff frequencies of 5.3 GHz for the PBT's with pn-junctions are reached. The PBT's with Schottky gates reach 7 GHz, however, with a lower breakdown voltage. A simple...
Interdigitated microwave bipolar transistors with submicron dimensions have been manufactured to study the effects that occur when the emitter width is reduced to values well below one micron. The DC current gain normalized to the total emitter area shows an optimum as a function of emitter width for 0.5 ??m wide emitters. The sidewalls of the emitters contribute significantly to the measured reverse...
Adding more functions to a logic circuit requires new process modules in the standard CMOS technology. Solutions for different memory types and analog circuitry are reviewed and the compromise between technical performance and additional processing cost will be shown.
A silicon bipolar technology, which uses Selective Epitaxial Growth (SEG) for the active base and collector regions is described. Key features of the SEG transistor configuration are a quasi self-aligned base/collector structure and an epitaxial base process, which has been integrated into a self-aligned double-poly emitter/base configuration. The high speed capability of the SEG transistor concept...
The narrow emitter effect associated with the self-aligned silicidation of the emitter and base regions of an advanced single-polysilicon bipolar transistor structure is analysed. This effect is shown to arise from an increased electron recombination at the periphery of the emitter, due to the proximity of the silicided base contact to the emitter edge. The impact of this phenomenon on the scaling...
A new procedure is described to separate the minority carrier current through the monosilicon/interface/polysilicon structure according to the various mechanisms. These mechanisms are then related to various processing conditions for process optimization. For the first time a significant effect of the monosilicon doping on the interface recombination has been identified.
The presented paper shows the necessity of sophisticated interconnection technology on VLSI and especially on forthcoming ULSI chips. New techniques have to be developed. The wire delay will become a significant problem on the way to a 0.25um technology.
A review is given of our recently improved physical models for device simulators. They have been implemented in MEDICI and MINIMOS. Examples of actual MOS and Bipolar transistors as well as more exploratory transistor structures will be presented. The physical insight obtained from these device simulations is used in our compact transistor models. Their strength and large validity range will be illustrated.
This paper reports on 2D Monte Carlo simulation of two logic inverters. A CML gate is simulated in commutation regime to study the evolution of the propagation delay as a function of the circuit time constants. Furthermore the behaviour of a CMOS inverter under radiation is analyzed.
A new two-transistor memory cell concept for 16-Mbit DRAM and beyond is described. This cell offers the advantages of small cell size, non-destructive and fast operation of reading with a built-in amplifier, and the capability of storing multiple-valued or analog information.
We report for the first time an analysis of impact ionization phenomena occurring in a complementary charge injection transistor. We observed the real-space transfer of minority carriers generated by impact ionization and collected by the collector contact. From the measured collector current and by means of a simple model, we estimated the electron impact ionization coefficient of In0.53Ga0.47As...
We have used a new selective CVD TiSi2 in an advanced CMOS process. Subhalf-micron transistors have been characterised, with results equivalent to devices made with more conventional salicide. Ring oscillators with typical gate a delay times have been fabricated. Finally, fully functional 16K SRAMS and 350 KT ASICs have been fabricated, which indicates the possibility of using this new process for...
A new highly reliable 3.3V only EEPROM cell technology has been developed. Using this cell concept and technology, a 9.5??2 cell has been manufactured in 0.8?? design rules. Further scaling will lead to a 5??2 cell in 0.5?? design rules. It is also possible to construct the cell without the access transistor [3]. This lead to another 10 to 15% cell size reduction making the cell competitive in size...
Based on device simulations an analytical DC-and AC-model for vertical DMOS transistors has been developed. It is based on a subcircuit approach. An enhanced MOS model for the channel and an adapted JFET model which accounts for drift velocity saturation in the drift region are used. As in existing approaches both the nonconstant doping in the channel region and the AC-behavior of the DMOS have not...
A high frequency, double polysilicon bipolar transistor technology on SIMOX is presented. The SOI substrate consists of a conventional SIMOX wafer upon which a twin epi-layer is grown. A high-frequency bipolar transistor technology is then transferred to this substrate. The initial experimental results are presented and show a high cut-off frequency of some 12.4 GHz. A comparison with identical devices...
In this paper, the correlation between noise figure degradation and the degradation of DC characteristics during emitter-base reverse stress is studied. It was found that the generation-recombination centers, which introduce emitter-base reverse stress, have an influence on high-frequency noise characteristic degradation.
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