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This paper discusses the low-frequency noise behaviour in partially depleted SOI MOSFETs. It is shown that while the noise in linear operation is little affected by using the twin-gate structure, a drastic reduction of the kink-related excess noise is observed, compared with a standard transistor. This reduction is explained by considering a recently proposed model for the low-frequency noise overshoot...
This paper discusses the low-frequency noise behaviour corresponding to Random Telegraph Signals in submicrometer Si MOSTs. It is shown that when the noise spectral density is measured as a function of the gate voltage (linear operation) or of the drain voltage, peak-shaped features are generally obtained. This excess-noise peak can be used to identify the occurrence of RTS, for instance in Silicon-on-Insulator...
First results on low-frequency noise (250 Hz-100 kHz) and microwave noise parameters (4 GHz-20 GHz) observed in a microwave Si/SiGe heterojunction bipolar transistors (1 ??m ?? 20 ??m) featuring current gain cut-off frequency of 90 GHz and a maximum oscillation frequency of 30 GHz are reported and discussed. All measurements have been performed on wafer using dedicated techniques.
An analysis of current situation in silicon carbide R&D shows that it is most real to fabricate SiC IMPATT diode on an epitaxial pn structure grown on the (0001)Si face of 6H-SiC crystal. The operating frequency of this diode will be in the range 90-250 GHz. We calculated numericallydynamic characteristics of the SiC IMPATT diode for pulse mode of operation at the frequency 140 GHz. Results show...
An efficient way to calculate 3-D stress distributions in silicon around embedded structures caused by different thermal expansion coefficients between silicon and inclusion is presented. The computational method is based on the solution for a parallelepiped, which is extended to arbitrarily shaped embedded structures.
The low-frequency noise in SOI MOSFET's is studied experimentally and by numerical simulations. The behaviors of devices with completely depleted and partially depleted silicon film are investigated for various substrate biases. The importance of volume inversion in thin Si film is underlined. Moreover, the variations of the current noise around the kink is analysed for thin and thick film devices...
In this paper we review some recent advances made in the field of dopant diffusion modelling in the various materials related with Si CMOS technology. After some information on diffusion in polycrystalline Si, SiO2, and silicides, we develop in more details the case of single crystal Si. A physical model able to handle the interactions between the diffusing dopant and the point defects is briefly...
The aim of this paper is to present a physically based numerical model for TiSi2 growth. After a description of the model which has been developed, some results on kinetics will be presented for 1D simulation. Finally, 2D simulations will be analysed with more focus on local effects around spacers in LDD CMOS technology.
This paper presents quantitative 2D stress dependent simulations of the Sealed Interface Local Oxidation (SILO) structure. In the SILO structure, the oxidation mask consists in a NitrideI/Oxide/Nitride II stack, in which the thin Nitride I layer is directly sealed on the silicon surface. A very thin oxide layer is considered between the silicon and the nitride-I layer in which the oxidant diffusivity...
In order to fabricate metal-insulator-semiconductor (MIS) devices with gate insulating films thinnest than 5 nm, organic monolayers have been grafted on the native oxide layer of silicon wafer. We demonstrate for the first time that a single monolayer of alkyl-trichlorosilane with a thickness in the range 1.9-2.8 nm allows to fabricate a silicon based MIS device with gate leakage current density as...
The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
A silicon bipolar technology, which uses Selective Epitaxial Growth (SEG) for the active base and collector regions is described. Key features of the SEG transistor configuration are a quasi self-aligned base/collector structure and an epitaxial base process, which has been integrated into a self-aligned double-poly emitter/base configuration. The high speed capability of the SEG transistor concept...
BF implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is investigated for the fabrication of shallow pnp polysilicon emitter bipolar transistors. The use of RTA, instead of furnace annealing, is shown to give shallower junctions, with a higher doping concentration at the polysilicon/silicon interface. The effect of fluorine, which is introduced into...
A new procedure is described to separate the minority carrier current through the monosilicon/interface/polysilicon structure according to the various mechanisms. These mechanisms are then related to various processing conditions for process optimization. For the first time a significant effect of the monosilicon doping on the interface recombination has been identified.
An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 ??m CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 ??m...
This communication deals with a new technique for completely characterizing the equivalent thermal circuit of a laser diode and its assembling structure. This method is able to give informations about the thermal resistances and capacitances of the various parts of the whole solid composed by the laser diode, the solder layer and copper submount. Experiments performed on BRS and DFB lasers have shown...
This paper reviews recent progress in high-speed Si/Si1-xGex heterojunction bipolar transistors. The values of fT and ECL gate delay achieved with these devices are described and compared with results for silicon homojunction bipolar transistors. The technological problems associated with the use of Si1-xGex are discussed, and device and circuit modelling results are presented which highlight the...
This paper describes the effects of the base/collector-heterojunction on large and small signal behaviour of a Si/SiGe/Si double heterojunction bipolar transistor (DHBT). Device simulations as well as circuit simulations help to explain the occuring effects and show their consequences.
By means of two-dimensional device simulation the influence of the Ge fraction (x) in the base of Si/Si1-x, Gex-HBTs on the transit frequency is investigated. The calculated results are compared to experimental data.
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