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Modeling of advanced isolation techniques for deep submicron technologies is described. Initially, calibration of stress-dependent parameters is done. The latter are used for comparing wet and dry, conventional and poly-buffered LOCOS isolations. Computer simulations were used to optimize isolation process.
This paper presents quantitative 2D stress dependent simulations of the Sealed Interface Local Oxidation (SILO) structure. In the SILO structure, the oxidation mask consists in a NitrideI/Oxide/Nitride II stack, in which the thin Nitride I layer is directly sealed on the silicon surface. A very thin oxide layer is considered between the silicon and the nitride-I layer in which the oxidant diffusivity...
An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 ??m CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 ??m...
The pwell implant and anneal for a 0.4μm CMOS process have been optimized for a self-aligned twin well without channel stop implant to yield improved n+ to nwell spacing, reduce the poly field NMOS leakage and make the process less sensitive to latch-up.
Field isolation for Ultra Large Scale Integration devices is evolving towards product adapted architectures. Specific solutions can be used for memory or bipolar devices that we distinguish from standard logic CMOS/BiCMOS devices for which Poly Buffer LOCOS, SILO and shallow trench isolations are taken as examples.
The growth of silicon dioxide in pure N2O has been evaluated by using conventional furnace oxidation method. The results have pointed out that neither lightly-doped nor heavily-doped substrates exhibit any self-limited growth behavior. The growth kinetics can be described by the linear-parabolic model. Enhanced oxidation has also been observed on heavily arsenic doped substrates in the pure N2O ambient.
This paper describes the fabrication of polysilicon / SiO2 / 6H silicon carbide structures with four different types of thin gate oxides. Wet and dry thermal oxidation, plasma-enhanced chemical vapor deposition (PECVD), and also an alternative method, oxidation of e-beam evaporated silicon, have been investigated. The four oxides were compared using capacitance-voltage measurements and breakdown field...
Dielectric reliability is of critical importance in the manufacture of double polysilicon floating gate EEPROM devices. This paper reports the effect of different polysilicon oxidation and doping conditions on the properties of both the inter-poly oxide and the tunnel oxide. The paper shows that increasing the polysilicon oxidation temperature results in an improvement in inter-poly oxide breakdown...
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