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We have compared in terms of drivability and reliability different LDD structures for 0.35 μm NMOS transistor. The sensitivities of device performance and hot carrier degradation to the LDD implant tilt angle and dose were measured and evaluated. The results indicate that LArge-Tilt-angle Implanted Drain (LATID) with high dose provides a well-optimised device.
Deep submicron MOSFETs with ultra shallow LDD junctions display a new mode of degradation previously not observed. The evolution of the substrate current with hot carrier stress is identified as a sensitive parameter for the degradation of ultra-shallow LDD devices. The cause for this new degradation mode is due to the fact that the oxide damage created during stress affects the field and current...
The gate-to-drain overlap effects on the hot carrier induced degradation of submicron LDD p-MOSFET's are investigated for the first time. Experimental results from three different structures, namely: 1) the reentrant poly gate, 2) the graded-gate-oxide and 3) the well overlapped gate and drain, are presented. We found that the weak overlap of an p-MOSFET improves the hot carrier immunity which is...
The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 μm LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this improved hot-carrier reliability. The maximum supply...
In this paper, the degradation of p+ and n+ poly p-MOSFET devices of a 0.5 μm technology is studied in detail. The former devices exhibit intrinsically a better hotcarrier hardness. The difference in hot carrier behaviour between the p+ and n+ poly transistors is attributed mainly to the short channel effect. The p+ poly devices are therefore more suited for the realisation of deep submicron devices.
This study reports the gate-voltage dependence of Large-Angle-Tilt Implanted Drain (LATID) and standard Lightly Doped Drain (LDD) technologies of 0.5??m effective channel-length suitable for 5V operation. It is found that although the strong lateral field reduction improve the LATID performance, acceptor-like oxide traps are revealed in the whole stressing gate-voltage range, a large spread of oxide-traps...
The device structure and the device design methodology to achieve the low voltage-low power sub-0.1 μm MOS devices are discussed. It is shown in the simulation that it is difficult to simultaneously satisfy two requirements to suppress the short channel effect and to improve the device performance in the sub-0.1 μm devices. It is experimentally demonstrated that the short channel effect can be sufficiently...
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