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The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
A review is given of our recently improved physical models for device simulators. They have been implemented in MEDICI and MINIMOS. Examples of actual MOS and Bipolar transistors as well as more exploratory transistor structures will be presented. The physical insight obtained from these device simulations is used in our compact transistor models. Their strength and large validity range will be illustrated.
We report for the first time an analysis of impact ionization phenomena occurring in a complementary charge injection transistor. We observed the real-space transfer of minority carriers generated by impact ionization and collected by the collector contact. From the measured collector current and by means of a simple model, we estimated the electron impact ionization coefficient of In0.53Ga0.47As...
The trencd towards ever decreasing geometries is making the non-volatile memory cell design task increasingly difficult. For reduced cost and time to market, simulation tools are essential to reduce the number of experiments on silicon wafers which are becoming increasingly expensive due to the increase in process complexity with each new generation [1]. A general purpose two-dimensional device simulator...
Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1.??m. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results...
We have performed a study of differently shaped InGaAs/InGaAsP quantum wells (Lz = 10 nm) with a view to finding the structure which produces the largest quantum confined Stark shift. We find both theoretically and experimentally that our greatest shift is produced by the structure composed of stepped quantum wells.
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