The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An analysis and modeling of the low frequency noise characteristics of deeply submicronic CMOS devices is conducted. It is shown that the scaling down of the gate area leads to dramatic change of the noise nature and to a substantial increase of the noise level dispersion. A generic modelling of the noise amplitude and spectrum is worked out as a function of geometry and biases, allowing a good representation...
Adding more functions to a logic circuit requires new process modules in the standard CMOS technology. Solutions for different memory types and analog circuitry are reviewed and the compromise between technical performance and additional processing cost will be shown.
CMOS latch-up parameters are experimentally studied in the context of deep submicron technology optimization. Holding voltage and triggering current values are measured for both various design rules (N+/P+ distance, structure width) and various process conditions (epitaxial thickness, substrate resistivity, well dose). It is demonstrated that with diffused well, latch-up free behavior can be obtained...
CMOS devices with 0.25μm physical gate lengths were fabricated on 200mm wafers utilizing a twin well, double level metal, fully planarized process. Single work function n+ poly silicon was chosen as the gate electrode for its ease of manufacturability. Deep UV lithography was used to define the critical layers; Poly, Contacts, Metal 1, Vias and Metal 2. All other levels were exposed using i-line lithography...
This paper reports on 2D Monte Carlo simulation of two logic inverters. A CML gate is simulated in commutation regime to study the evolution of the propagation delay as a function of the circuit time constants. Furthermore the behaviour of a CMOS inverter under radiation is analyzed.
In order to achieve the high-speed operation of scaled CMOS devices, low source-drain and gate resistivity is required. However, an abrupt increase in TiSi2/polysilicon resistance occurs when the line width falls below 0.25??m. We analyze this degradation and indicate that NiSi is a suitable candidate to replace TiSi2, because in the case of NiSi no resistance degradation occurs.
DMILL technology is being developped for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva) [3]. Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2 ??m thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric...
A new type of precision thinned bonded silicon wafer is evaluated for thin film CMOS/SOI applications. SOI wafers with silicon film thickness variations of less than ??2.5 nm are available with choice of substrate doping and buried oxide thickness. CMOS devices fabricated on these wafers have the same carrier mobilities as comparable bulk silicon MOSFETs.
This paper provides a state of the art review of BICMOS processes. It explains why and how BICMOS technology is becoming strategic for some sectors in the near future. After a short presentation of market dynamics in key applications, a deep analysis of the evolution of BICMOS technology will be done. Emphasis is placed on trade offs between functionalities - performances and complexity-cost. Then...
This paper describes a smart power device which uses a vertical 600 V, 10 A IGBT as a power switch and a signal and control circuit fabricated with a 2 ??m SOI-CMOS technology. The dielectric isolation between the IGBT and the control circuit is formed by SIMOX (separation by imlanted oxygen) and LOCOS technology. A self protection is achieved by measuring load current and device temperature. The...
Technology evolution pushes the traditional 5 volts VDD of devices to lower voltage values and in the meantime new Low Power applications are emerging, mainly in the ``anytime, anywhere'' communications area.
A CMOS circuit is presented which performs all analog interface functions to a standard telephone subscriber line including DC and AC termination, send and receive amplification, anti-side-tone network, line loss compensation, and dialing control. All transmission parameters are software programmable and are loaded into the IC during hook-off or, if necessary, during conversation. It is fabricated...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.