The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
The trencd towards ever decreasing geometries is making the non-volatile memory cell design task increasingly difficult. For reduced cost and time to market, simulation tools are essential to reduce the number of experiments on silicon wafers which are becoming increasingly expensive due to the increase in process complexity with each new generation [1]. A general purpose two-dimensional device simulator...
Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1.??m. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.