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The behavior of several innovative submicrometer Si/SiGe FET variants is characterized using 2D numerical simulation. The behavior that is investigated includes transconductance, cutoff frequency, subthreshold and breakdown characteristics. The benefits of graded Ge doping in the channel is clearly demonstrated. MOS gated devices are predicted to have transconductances and cutoff frequencies about...
Several 1-D analytical models of the potential distribution across the nMOS/GAA device are proposed and compared. The most accurate result is achieved solving the Poisson equation accounting for both the depletion charges and an approximation of the electron density at the surface of the film. The derived analytical expressions of the drain current and the threshold voltage are in good agreement with...
We have studied the effect of technological parameters on the performances of an ultrashort Si-NMOS transistor, at room temperature, using 2D Monte Carlo simulation. Results obtained for a device with source-drain extensions are compared with experiments. Doping profiles of Gaussian form are assumed. The main physical phenomena involved in the device behaviour are described. Additionally, electrical...
A new ??-doped GaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor(HEMT) utilizing a graded In composition in InxGa1-xAs quantum well grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) was demonstrated. For a gate geometry of 2 ?? 100 ??m2, the studied new structure revealed superior extrinsic transconductance and saturation current density of 175 mS/mm and 500 mA/mm...
The gate-to-drain overlap effects on the hot carrier induced degradation of submicron LDD p-MOSFET's are investigated for the first time. Experimental results from three different structures, namely: 1) the reentrant poly gate, 2) the graded-gate-oxide and 3) the well overlapped gate and drain, are presented. We found that the weak overlap of an p-MOSFET improves the hot carrier immunity which is...
The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 μm LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this improved hot-carrier reliability. The maximum supply...
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