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The design, fabrication and characterization of a high performance 0.15 μm n-channel and p-channel MOS devices for room temperature operation are described. The design features 5 nm gate oxide, shallow source-drain junction extensions, thin self-aligned titanium silicides, and highly doped wells with low impurity channels for providing low threshold voltages and good turn-off characteristics. A reduced...
We have compared in terms of drivability and reliability different LDD structures for 0.35 μm NMOS transistor. The sensitivities of device performance and hot carrier degradation to the LDD implant tilt angle and dose were measured and evaluated. The results indicate that LArge-Tilt-angle Implanted Drain (LATID) with high dose provides a well-optimised device.
The pwell implant and anneal for a 0.4μm CMOS process have been optimized for a self-aligned twin well without channel stop implant to yield improved n+ to nwell spacing, reduce the poly field NMOS leakage and make the process less sensitive to latch-up.
We have used a new selective CVD TiSi2 in an advanced CMOS process. Subhalf-micron transistors have been characterised, with results equivalent to devices made with more conventional salicide. Ring oscillators with typical gate a delay times have been fabricated. Finally, fully functional 16K SRAMS and 350 KT ASICs have been fabricated, which indicates the possibility of using this new process for...
In a 3-dimensional integrated magnetic sensor cross-axis sensitivities among the various components of the magnetic field have been a practical design problem. This paper describes the elimination of any cross-sensitivity if a 3-dimensional magnetic sensor is implemented in BiCMOS technology. A device is designed and fabricated by placing a split-collector magnetotransistor and a split-drain MOSFET...
The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 μm LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this improved hot-carrier reliability. The maximum supply...
This paper describes a smart power device which uses a vertical 600 V, 10 A IGBT as a power switch and a signal and control circuit fabricated with a 2 ??m SOI-CMOS technology. The dielectric isolation between the IGBT and the control circuit is formed by SIMOX (separation by imlanted oxygen) and LOCOS technology. A self protection is achieved by measuring load current and device temperature. The...
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