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Over the past two decades the scaling of IC technologies has reduced device dimensions by more than 20-fold. In the process of this scaling many reliability and parasitic effects have come to dominate the technology design process. Certainly MOS gate reliability and substrate currents (both due to impact ionization and junction leakage) are of major concern. This paper discusses the parasitic effects...
The presented paper shows the necessity of sophisticated interconnection technology on VLSI and especially on forthcoming ULSI chips. New techniques have to be developed. The wire delay will become a significant problem on the way to a 0.25um technology.
A general overview is presented of high density packaging methods earmarked for use with future leading edge integrated circuits. Pertinent design, performance and cost factors are compared relative to future circuit requirements.
This paper investigates isolation and wiring in a typical 700-1000-V, junction isolated (JI), high voltage integrated circuit (HVIC), process. It proposes a novel technique for running 1000-V wires over the isolation to other parts of the chip, without causing breakdown of the isolation itself or inducing unwanted parasitics.
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