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Based on device simulations an analytical DC-and AC-model for vertical DMOS transistors has been developed. It is based on a subcircuit approach. An enhanced MOS model for the channel and an adapted JFET model which accounts for drift velocity saturation in the drift region are used. As in existing approaches both the nonconstant doping in the channel region and the AC-behavior of the DMOS have not...
The goal of this paper is to present some design rules for a high voltage, up to 1200 V, Vertical Double diffused MOS (VDMOS) transistor using a semi-resistive field plate (such as SEPOS: Semi-Insulating POlycrystalline Silicon) as a termination technique and as a passivation. The evolution of breakdown voltage versus critical parameters, such as epitaxial doping and thickness, field plate length...
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