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Hot-carrier (HC) degradation of analog operation parameters has been investigated by stressing LDD-n-MOSFETs with channel lengths of 1.0 - 5.0 ??m. A model has been developed to clarify the different mechanisms leading to degradation of the differential drain output resistance. Experimental evidence is given to check the model. Finally, possible consequences in the circuit environment are discussed.
The narrow emitter effect associated with the self-aligned silicidation of the emitter and base regions of an advanced single-polysilicon bipolar transistor structure is analysed. This effect is shown to arise from an increased electron recombination at the periphery of the emitter, due to the proximity of the silicided base contact to the emitter edge. The impact of this phenomenon on the scaling...
In this paper, the correlation between noise figure degradation and the degradation of DC characteristics during emitter-base reverse stress is studied. It was found that the generation-recombination centers, which introduce emitter-base reverse stress, have an influence on high-frequency noise characteristic degradation.
In this paper, the degradation of p+ and n+ poly p-MOSFET devices of a 0.5 μm technology is studied in detail. The former devices exhibit intrinsically a better hotcarrier hardness. The difference in hot carrier behaviour between the p+ and n+ poly transistors is attributed mainly to the short channel effect. The p+ poly devices are therefore more suited for the realisation of deep submicron devices.
This study reports the gate-voltage dependence of Large-Angle-Tilt Implanted Drain (LATID) and standard Lightly Doped Drain (LDD) technologies of 0.5??m effective channel-length suitable for 5V operation. It is found that although the strong lateral field reduction improve the LATID performance, acceptor-like oxide traps are revealed in the whole stressing gate-voltage range, a large spread of oxide-traps...
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