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In order to fabricate metal-insulator-semiconductor (MIS) devices with gate insulating films thinnest than 5 nm, organic monolayers have been grafted on the native oxide layer of silicon wafer. We demonstrate for the first time that a single monolayer of alkyl-trichlorosilane with a thickness in the range 1.9-2.8 nm allows to fabricate a silicon based MIS device with gate leakage current density as...
The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
The growth of silicon dioxide in pure N2O has been evaluated by using conventional furnace oxidation method. The results have pointed out that neither lightly-doped nor heavily-doped substrates exhibit any self-limited growth behavior. The growth kinetics can be described by the linear-parabolic model. Enhanced oxidation has also been observed on heavily arsenic doped substrates in the pure N2O ambient.
With the purpose of determining material parameters of MOS-technology dedicated Shockley-Haynes-structures and MOS varactors, among others, have been integrated on a single chip. By use of a specially developed electronic unit an improved performance of the Shockley-Haynes-Experiment has been achieved. In this paper from the comparison of measurements and analytic simulations the hole mobility ??p...
DMILL technology is being developped for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva) [3]. Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2 ??m thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric...
A new type of precision thinned bonded silicon wafer is evaluated for thin film CMOS/SOI applications. SOI wafers with silicon film thickness variations of less than ??2.5 nm are available with choice of substrate doping and buried oxide thickness. CMOS devices fabricated on these wafers have the same carrier mobilities as comparable bulk silicon MOSFETs.
This study characterizes the SiO2 etching by two gases C2F6 and CF4, in an experimental high-density reactor. The effect of some experimental parameter variations on the etching rate and F and CF2 radical concentration, has been studied and correlated to the self-induced voltage and the substrate temperature.
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