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On behalf of the Technical Program Committee, we are pleased to welcome you to the 2nd Microsystems and Nanoelectronics Research Conference (MNRC 2009). In addition to the opportunity to learn about research achievements and challenges in the areas of microsystems and nanoelectronics, this event provides a unique opportunity for the promotion and development of graduate students and their research.
On behalf of the MNRC2009 Steering and Technical Program Committees, it is my privilege to welcome you to the 2nd Microsystems and Nanoelectronics Research Conference (MNRC 2009) - an event collocated with CMC Microsystems' Annual Symposium. The conference intent is to promote synergy among researchers and accelerate excellence in graduate student research.
This paper proposes a remote frequency calibration method that allows a passive wireless transponder to adjust the frequency of its local oscillator to a desired value using an injection-locked phase-locked loop (IL-PLL). The relaxation oscillator of the proposed IL-PLL employs a current pulse generator to generate the effective hysteresis needed for oscillation without using a Schmitt trigger. Integrating...
A CMOS 3.1–10.6GHz low power low noise amplifier utilizing a feedback technique is reported. The series-inductive peaking has been used in the output stage to improve the 3-dB bandwidth of the LNA. To achieve wide and stable power and noise matching, the frequency dependent Miller multiplication factors, combined with a new parallel input inductor, is employed. The design is implemented in standard...
Two metamaterial-inspired CMOS integrated circuits for millimetre-wave frequencies of operation are investigated that utilize lumped element components and tuneable varactors in an LC ladder configuration for negative group delay (NGD) values. Measurement and simulation results of a passive, fixed transmission line (TL) structure are presented along with an equivalent circuit model. Realized NGD values...
Simulation of the temperature distribution in a regular IC interconnect network is achieved by means of an analytical-symbolic approach. Analytical Joule heating solutions along each interconnect can provide accurate solutions with far fewer nodes than numerical solutions. Multiple evaluations, including iterating temperature-dependent thermal conductivity to achieve a self-consistent solution, scale...
This paper presents an opto-electrical receiver with on-chip photodetector in 0.18-µm CMOS technology. By combing a spatially modulated light detector and an analog equalizer, a maximum data rate of 5 Gbps is achieved. The responsivity of the photodetector is 0.052 A/W. Occupying a core area of 0.72 mm2, the fully integrated opto-electrical receiver achieves 4.25 Gbps and 5 Gbps with a power consumption...
The design and fabrication of a laterally-coupled distributed feedback (LC-DFB) laser using a third order grating is presented. The side mode suppression ratio is at least 45 dB for as-cleaved devices with various cavity lengths. We numerically investigate three approaches to reducing the threshold current.
This paper describes a novel design of an indirect-heating thermal actuator with integrated capacitive position sensor. The displacement of the actuator provided by the sensor enables a feedback control capability. The analytical model and finite element analysis (FEA) are presented to validate the design concept. The devices were fabricated using MetalMUMPs process. The experimental result shows...
An electrostatic micro-power generator (MPG) designed to power wireless sensors is presented. The MPG does not need an initial charge source and produces 9µW using a 0.5g vibration source. The MPG is also characterized by wide energy collection band that can reach up to 10Hz. Optimization of a prototype shows the possibility of generating more than 190µW. A non-linear model for the proposed MPG is...
An integrated RF microelectromechanical systems (MEMS) tunable impedance matching network is presented for use in CMOS adaptive amplifiers. The matching network is based on high quality factor (Q) parallel-plate MEMS tunable capacitors implemented by standard 0.18-µm CMOS technology. A reconfigurable amplifier for WLAN applications operating at 5.2 GHz is designed and implemented. The amplifier achieves...
The effect of single event transient is examined in a 64-bit logarithmic adder. Pseudo-static logic (PSL) is proposed to be an area efficient logic choice for time redundant circuit design. The proposed adder is capable of detecting 81% of the errors working at 2.4 GHz consuming 42mW of power. The detection capability comes at the expense of 19% power penalty and negligible area overhead. The results...
Reduced clock-swing flip-flops are very attractive in high-performance deep-pipelined systems since significant power reduction can be achieved with minimal performance degradation. In this paper, a new reduced clock-swing pre-discharge flip-flop (RCSPDFF) is proposed. The performance advantage of RCSPDFF comes from the fact that its critical path is reduced significantly to only four transistors...
We propose an impulse flip-flop and a true single-phase clock (TSPC) flip-flop that are soft error robust. Each flip-flop consists of a unique transfer unit and a soft error robust 8-transistor Quatro latch. The transfer unit of the impulse flip-flop uses the clock signal and its complement to generate a narrow voltage pulse that enables writing the data into the Quatro latch. In contrast, the transfer...
This paper presents a low power 12-bit 10MS/s algorithmic analog-to-digital converter (ADC) implemented in a 130-nm CMOS technology. A technique is proposed for using capacitor scaling and capacitor sharing to reduce the power requirements of algorithmic analog-to-digital converters. The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66dB while consuming 1mW from a 1.5V supply.
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