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The effect of single event transient is examined in a 64-bit logarithmic adder. Pseudo-static logic (PSL) is proposed to be an area efficient logic choice for time redundant circuit design. The proposed adder is capable of detecting 81% of the errors working at 2.4 GHz consuming 42mW of power. The detection capability comes at the expense of 19% power penalty and negligible area overhead. The results...
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