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As CMOS scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full CMOS compatibility, such as Logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility...
The integration of today??s complex multi-power domain IOs, inherited from legacy ??Reuse IP?? sources, poses a big challenge to the full chip physical integration in terms of product cost and design cycle time for products such as Tolapai, the first IA based SoC with IA CPU core, South bridge (ICH), North bridge (MCH), acceleration hardware and networking interfaces. To meet these challenges, the...
In recent SOPC (System on Programmable Chip) design, a system becomes very complex and the cost of modifying the design during the development becomes very expensive. Based on the technology of the C to HDL (Hardware Description Language), we propose a framework to convert C++ class to hardware, which can be used to cope with the change of design requirement during the development period. Within this...
With the ever-increasing complexity and the cost on SoC??s verification, more attentions are paid to the hardware/software co-verification. In this paper, two HW/SW co-verification methods are compared between virtual-prototype machine and HW-board platform. A hardware platform on ARM-prototype system for an application-specific SoC??s HW/SW co-verification is implemented complied with software design...
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by...
This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 ??m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm2. The post-layout simulation results...
With the developing of the integrated circuit design and fabrication technology gradually, system-on-chip (SoC) technology has been widely used because of its high performance such as small size, low power consumption and so on. This paper describes a digital three-phase SPWM signal generation SoC based on OpenRISC1200, a 32-bit RISC processor core. The system integrates parameter controlling, displaying...
This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage...
A BIST scheme that can both characterize the dynamic and static parameters of ADCs in Mixed-Signal SoCs are proposed in this paper. This approach can be implemented almost all digitally except for a few simple analog filters. Analog stimulus for both the dynamic and static test are encoded and stored in on-chip RAM or ROM and retrieved when the corresponding test starts. Elemental operative units...
This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology,...
A set of SoC low power design methods is presented based system level, IP module level and gate level. These methods were applied to low power design of a SoC. The SoC power simulation results showed that the static and dynamic power of this SoC was quite low. The goals of the low power design methods applied on the design were achieved. The SoC has been implemented in 0.18 ??m COMS process, the area...
With the dramatic increase in size and complexity of systems on chip (SoC), there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction, one approach is to place macros around the boundary of chip and the remainder is used for arrangement of standard cells. To deal with such kind of placement,...
A promising combination of the semiconductor integrated system-on-a-chip (SoC) with the lab-on-a-chip (LOC) is brought in this paper. In this paper, we propose a new technology which enables monolithic integration of the self-assembled biological system, the MEMS structure, the microfluidic system, and CMOS electronic circuits together. Utilizing this approach, more functionality is introduced into...
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