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Based on 3D statistical device simulation, the impacts of key statistical variability (SV) sources (in both individual and combined forms) on device characteristics are studied in detail for a 32 nm thin-body SOI technology. The corresponding impacts on SRAM cell stability are presented as well. The simulation results indicate that thin body architectures are not only resistant to random discreet...
The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of...
Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell??s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor??s I-V characteristics, but also faithfully reproduce ICRITs?? behavior of the cell as a whole. A...
The effects of random dopant fluctuations (RDF) on the static noise margins (SNM) of 6-T SRAM cells are analyzed by using a doping sensitivity approach. The approach presented in this article is based on a full circuit perturbation theory at the level of each device transport model. The bias points and the magnitude of random dopant induced fluctuations are computed by solving the Poisson, current...
A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows...
SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM??s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis...
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45??-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current...
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early...
For the new technology development, normal yield improvement methods useful to production are not enough. In the early phases, without yield signature, many systematic issues can not be captured by WAT or inline defect inspections. We need to create new analysis methods based on the technology development different phases. At the same time, multiple issues usually mix together and are not easy to...
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that...
This paper presents a novel build-in-self-test (BIST) manufacture-oriented interconnect test strategy of SRAM-based field programmable gate arrays (FPGA). Programmable switches (PSs) and line segments are tested separately, which is different from previous methods. An improved depth-first-search (DFS) algorithm is developed for automatically deriving minimal or near minimal test configuration patterns...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Inverse Lithography Technology (ILT) is a promising solution to enhance the resolution of the optical system in deep-subwavelength lithography. In this paper, we introduce a gradient-based framework for mask synthesis. Firstly, we model the mask-to-wafer process using a continuous transfer function. Then Newton iterations are employed to solve the continuous inverse problems. Finally, we apply our...
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