If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early monitor of yield degradation due to eSiGe and therefore an effective vehicle for optimization between yield and performance. Using this monitoring structure, an eSiGe process optimized for yield was developed which does not show additional yield loss due to eSiGe while retaining comparable performance enhancements.
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.